The 555, from Transistors · Reference
Every term this course uses, defined once and used with exactly this meaning throughout. Experiments link here on a term's first appearance.
A circuit with two inputs (V+ and V−) and one output. The output goes high when V+ > V− and low when V+ < V−. It answers one question: which input is bigger?
Why it matters: the 555 needs two: one watching for the timing capacitor to climb past 2/3 VCC (3.33 V), one watching for it to fall below 1/3 VCC (1.67 V). Experiments 3–8 build one comparator from bare transistors.
The input voltage at which a circuit's output switches state. A true comparator's threshold is set by whatever you connect to its second input; a one-transistor switch's threshold is stuck at VBE.
Base–emitter voltage of a bipolar transistor. A silicon BJT starts conducting meaningfully around 0.6–0.7 V, and VBE drifts about −2 mV per °C as the transistor warms.
Why it matters: that drift is one of the three reasons a single transistor makes a poor comparator, and the reason the differential pair exists.
The standard model of how a bipolar transistor behaves: collector current climbs exponentially with VBE: very roughly a factor of ten for every extra 60 mV. It is why VBE barely moves while the current swings over decades, and why a transistor makes such a sharp switch.
Why it matters: that exponential is the engine under everything in the comparator experiments: it is what lets a differential pair steer its tail current so decisively (Experiment 4) and a current mirror copy a current so faithfully (Experiment 5).
The three operating regions of a BJT: cutoff (off, no collector current), active (collector current proportional to base current: amplifier territory), and saturation (fully on, collector pulled near the emitter, where more base current changes nothing).
Why it matters: a comparator wants to sprint through the active region as fast as possible. Active is the "mushy" zone where the output is neither high nor low.
A BJT with its emitter grounded (or held at a fixed rail), the input at the base, and the output at the collector through a load resistor. It inverts: base voltage up → collector voltage down.
Two matched transistors with their emitters tied together and fed by one shared current (the "tail"). The pair steers the tail current towards whichever transistor has the higher base voltage. It compares two voltages instead of comparing one voltage against VBE, and because both transistors drift together, the VBE drift cancels.
Why it matters: this is the heart of practically every comparator and op-amp design, including both comparators inside the NE555. Built in Experiment 4.
The shared emitter current of a differential pair. It can be set crudely by a resistor or precisely by a current mirror.
A circuit that pushes a set current through whatever it is connected to and holds that current steady regardless of the voltage across it: the mirror image of a voltage source, which holds voltage steady and lets the current vary.
Why it matters: a differential pair's tail wants a current source instead of a plain resistor, so the shared current stays flat as the inputs move together; the discrete 555 builds one as a current mirror in Experiment 5.
The band of input voltage over which a differential pair can actually sense a difference. It is fixed by the transistors' polarity: an NPN pair works from ~0.9 V up to VCC (its joined emitters sit one VBE below the inputs, and the tail source needs ~0.2–0.3 V of headroom above ground); a PNP pair is the mirror image, working from ground up to ~VCC − 0.9 V. Neither type spans the whole supply.
Why it matters: this is why the 555's trigger comparator (inputs near ground) is built from PNP transistors and its threshold comparator (inputs near VCC) from NPN. The direction of the output logic plays no part in that choice: it is set by wiring.
A differential pair's knack for ignoring a voltage applied equally to both inputs while still amplifying the difference between them. Perfect rejection means a disturbance shared by both inputs (supply wobble, a temperature shift) produces no change at the output. It is usually quoted as a ratio, the CMRR.
Why it matters: it is the same property, seen from the output, that lets a matched pair cancel VBE thermal drift in Experiment 4; a lone transistor has no common-mode rejection at all.
A two-transistor circuit that copies a reference current flowing in one branch into another branch. Used as a stable tail-current source, and later as an active load that multiplies a differential pair's gain.
Replacing a differential pair's plain collector load resistor with a current mirror, so each side is loaded by a near-infinite dynamic resistance instead of a few kΩ. The gain leaps, and the transition on the transfer curve goes from a mushy ramp towards a near-vertical cliff.
Why it matters: this is the trick that finally gives the discrete comparator comparator-grade gain, built and measured in Experiment 6, where it closes the low-gain flaw first found in Experiment 3.
The final buffer that takes a comparator's or latch's internal decision and drives the outside world, sourcing and sinking load current without letting the load drag the sensitive internal node around. The NE555 uses a push-pull pair here.
Why it matters: Experiment 7 adds a PNP output stage to cure the "output trapped near V−" flaw: the point where the bare stage can pull its output low but never cleanly high.
A plot of output voltage versus input voltage. A perfect comparator's transfer curve is a vertical cliff at the threshold; any circuit you can build has a slope, and the steeper the slope, the higher the gain.
Why it matters: your oscilloscope draws this directly in X-Y mode: input on X, output on Y.
How much the output changes per unit of input change: the slope of the transfer curve. A comparator is, structurally, an amplifier with very high gain and no feedback, so any tiny input difference slams the output to a rail.
How strongly a transistor or differential pair turns a change of input voltage into a change of output current: gm = ΔIC/ΔVBE, measured in siemens. Multiply gm by the load resistance and you have the voltage gain.
Why it matters: it explains why raising the load resistance wins so much gain: the same gm feeding an active load (Experiment 6) delivers far more output swing than it does into a small collector resistor.
A supply voltage. In this course the rails are +5 V and GND (0 V).
Two resistors in series across a supply, tapping a fixed fraction of it at their junction: the tap sits at R2/(R1+R2) of the rail. Stack three equal resistors and the taps land at exactly 1/3 and 2/3 of the supply: the 555's two reference voltages.
Why it matters: Experiment 9 builds this divider on the board in place of the temporary references from the bench supply, so the thresholds follow VCC.
A threshold or measurement expressed as a fixed fraction of the supply rather than an absolute voltage, so it scales with VCC on its own. The 555's trip points are ratiometric: always 1/3 and 2/3 of VCC, whatever VCC happens to be.
Why it matters: it is exactly why the on-board divider of Experiment 9 beats a bench-dialled reference: change the rail and the thresholds follow for free.
Making the switch-high threshold different from the switch-low threshold so the output can't chatter when the input sits near the threshold. The 555 gets its hysteresis from the flip-flop rather than from the comparators, so the discrete comparators built here won't need it.
A 555 wired to oscillate on its own with no stable resting state: it charges and discharges its timing capacitor forever between the 1/3 and 2/3 thresholds, emitting a continuous square wave.
Why it matters: the astable is the circuit you build with the NE555 in Experiment 1 and then rebuild from IC blocks and bare transistors across the whole course.
A 555 wired as a one-shot: it rests in one stable state until a trigger arrives, emits a single pulse of a set length, then falls back and waits. "Mono": one stable state.
Why it matters: it is the 555's other classic mode; seeing it beside the astable shows what the same comparator-and-latch core does when its capacitor is wired to fire once rather than cycle.
A circuit with two stable resting states, each holding until something actively flips it: in other words, a one-bit memory. The 555's flip-flop is bistable.
Why it matters: it is the heart of the timer's memory, built from cross-coupled NOR gates as the SR latch in Experiment 11; the "bi" is the two states that latch can hold.
The fraction of each cycle a square wave spends high, given as a percentage. A plain 555 astable can't quite reach 50%: charge and discharge share a resistor, so the high time always runs a little longer than the low.
Why it matters: it is one of the numbers you predict and then read off the scope on the reference 555 in Experiment 1, and it explains the lopsided output you measure there.
The oldest integrated logic family: inputs drive transistor bases through resistors, the output is a collector pulled up through a resistor, and logic levels are just "transistor saturated" (≈0) versus "transistor cut off, pulled up" (≈VCC).
Why it matters: every logic gate you build in Experiments 10–11 is RTL: the simplest thing that can possibly work, and historically the first choice (it flew in the Apollo Guidance Computer).
A logic gate whose output is high only when all inputs are low (NOT-OR). In RTL: two (or more) grounded-emitter transistors sharing one collector pull-up. Any input high saturates its transistor and drags the output down to VCE(sat), ≈0.1 V or less; a well-saturated switch measures a few tens of millivolts; the output rests at VCC only when every transistor is off. A single such transistor with one input is just an inverter (NOT gate).
Why it matters: the 555's entire memory is built from this one gate: two cross-coupled NOR gates make the SR latch. Built in Experiment 10.
A property of a logic operation meaning any Boolean function can be built from copies of it alone. NOR (and NAND) are each functionally complete, memory included.
Why it matters: why one gate type is enough: you never need a separate "memory part", only NOR gates wired to feed each other.
A one-bit memory: a Set input drives the output high and it stays high after Set is released; a Reset input drives it low and it stays low. Built from two cross-coupled NOR gates, each output wired back into the other's input.
Why it matters: this is the 555's flip-flop: the trigger comparator sets it (capacitor below 1/3 VCC), the threshold comparator resets it (above 2/3), and it holds the state in between. Built in Experiment 11.
A capacitor placed close across a circuit's supply and ground to act as a local charge reservoir, so when a stage suddenly draws current it is supplied right there instead of through long, inductive supply leads. Its effect is set by the loop inductance (lead length and loop area) rather than by the capacitance alone: a cap several centimetres away through a long jumper barely helps. Classic values: 0.1 µF (code 104) right at the device for fast transients, plus a bigger bulk cap (1–10 µF) nearby.
Why it matters: on the all-transistor breadboard 555 of Stage Three, the supply reaches the board through long leads, so a stage that switches suddenly can move the board's own rails. The board built in Stage Four has the fix in place: C1, a 0.1 µF 0805 across VCC and GND right at the header.
The local "ground" (or supply rail) momentarily shifting because a switching current flows through the finite resistance and especially inductance of the wiring (). When a noisy, high-current return shares a wire with a sensitive reference, that shift couples straight into the reference, so a clean signal looks noisy because the ground beneath it moved. Cured by short leads, small loops, and separating high-current returns from sensitive grounds (star grounding).
Why it matters: a thick trace on the oscilloscope can be a clean signal on a moving ground. It can also be the circuit oscillating: the thick traces of Experiment 7 came from an input transistor oscillating at the end of its instrument lead, and a 1 kΩ in series with each base removed them.
The output-load setting on the generator, telling it the load is high impedance (a breadboard circuit instead of 50 Ω). With the wrong setting, the amplitude at the circuit is double what the screen says. On the SDG1062X: hold the channel's Output key ~2 s to toggle it.
Why it matters: set this first, every session. It is the number-one cause of "my circuit sees twice the voltage I dialled in". Full keystrokes: the function-generator reference.
One electrically continuous connection: every pin, wire segment, junction and same-named label that touches, taken together as a single point. Two labels with the same name on the same sheet are the same net, wire or no wire. A net has exactly one voltage at a time.
Why it matters: in the master schematic (Experiment 14), THRESHOLD at Q1's base on the left and at header pin 6 on the right are one net; that is how the pin breakout works without wires running across the sheet.
The circuit reduced to pure connectivity: the list of parts plus, for every net, which pins belong to it. No positions, no drawing: the schematic is for humans, the netlist is the design of record. ERC walks it, SPICE executes it, the PCB editor routes it (the ratsnest is the netlist drawn as lines), and the gerbers are its copper shadow.
Why it matters: two schematics that look different but produce the same netlist are the same circuit; conversely, a wiring error that slips past visual inspection (a comparator built with the wrong input polarity, say) shows up at once in a netlist diff.
The copper-and-silkscreen pattern a specific physical part solders down to: pads sized and spaced for that exact package, plus its outline and reference designator. The schematic says what connects; the footprint says what it physically lands on.
Why it matters: Experiment 17 assigns a footprint to every symbol: the step that turns an abstract netlist into something a factory can actually build.
A component built to solder onto pads on the surface of a board, with no leads pushed through holes: smaller and cheaper than through-hole, and the whole ambition of Stage Four.
Why it matters: where many courses steer around surface-mount, this one walks straight at it: from Experiment 17 the 555 is rebuilt entirely from SMD parts and hand-assembled.
A tiny three-lead surface-mount package about 3 mm across: the standard home for a single small-signal transistor like the ones that make up the discrete 555.
Why it matters: every transistor on the Stage Four board lives in a SOT-23; Experiment 17 picks the footprints and the assembly experiments hand-solder them under magnification.
A bare copper pad on a net that has no pin, so that a probe tip can touch the net on the assembled board. Nothing is soldered to it.
Why it matters: the Stage Four board has five, TP1 to TP5, on S, R, Q, Q̄ and the 1/3 tap. Experiment 14 explains how they find the block with a fault.
A large, continuous area of copper on a PCB layer tied to ground, filling the space around the signal traces. It hands every return current a short, low-inductance path straight home and helps shield the signals above it.
Why it matters: Experiment 18 pours a ground plane: the board-level cure for the ground bounce and aerial-lead trouble first met on the breadboard in Experiment 9.
A plated-through hole that carries a connection from one copper layer of a board to another: the PCB's vertical wire.
Why it matters: Experiment 18 uses vias to stitch signals and the ground plane between layers as the 555 is laid out.
The tangle of thin straight lines the PCB editor draws between pads that share a net but aren't yet joined by copper: the netlist drawn as "still to wire". Each line disappears as you lay the matching trace.
Why it matters: it is the visual to-do list you work down while routing the board in Experiment 18.
The standard file set a board house reads to make your PCB: one file per layer (copper, soldermask, silkscreen and the rest), each just a list of 2-D shapes. The gerbers are the netlist's copper shadow, made manufacturable.
Why it matters: exporting the gerbers and checking them against the design is the last gate before the board is sent out, in Experiment 19.
An output that is just a transistor's collector with no load attached: it can pull down to ground (transistor on) but cannot drive high. Off means disconnected; it does not mean 5 V. The high state must come from elsewhere: a pull-up resistor, or a load the user supplies.
Why it matters: the discrete 555's OUT pin is open-collector by design. On the breadboard build, the LED and its 220 Ω from VCC were the output buffer's load; move the LED away and OUT is left open-collector; in the Experiment 16 SPICE smoke test an unloaded OUT floats to numerical garbage until a load (or pull-up) is added.
A resistor from a signal to VCC that defines the signal's idle state as high, while still letting any transistor easily win and pull it low. The value is a trade-off: smaller = a stiffer high and faster edges but more current when pulled low; 1 k–100 k are all common.
Why it matters: used all over the discrete 555: the latch nodes idle high through 1 k pull-ups, the trigger comparator's output through 4.7 k, and RESET idles inactive through 100 k. The reference design also puts a 4.7 k pull-up on OUT so pin 3 reads a clean 5 V when the output isn't sinking.
The internal net carrying the trigger comparator's decision into the latch. On the sheet: Q14's collector · pull-up R7 · R11 → Q18's base · test point TP1. Active-high: it snaps high when TRIG falls below 1/3 VCC, setting the latch (Q̄ low → OUT high, charging begins). It has no header pin; it is purely internal.
Why it matters: named on the master net table (Experiment 14) and load-bearing in Experiment 13: S is the path that can fight RESET (a drained capacitor fires the trigger), so the reset block's Q23 clamps the S wire to ground while reset is held.
S's twin: the internal net carrying the threshold comparator's decision. On the sheet: Q7's collector · R5 to GND · R8 → Q15's base · test point TP2. Active-high: it fires when THR rises above 2/3 VCC, clearing the latch (Q low → OUT low, discharge begins). Not to be confused with the RESET pin: the R net clears the latch every cycle as part of normal oscillation; pin-4 RESET is the external override.