Full Stack Electronics · Stage Three · Experiment 10

Experiment 10: The NOR Gate

Build the gate of the timer's memory from two transistors and three resistors. Then measure its output for all four combinations of its inputs.

Experiment 9 connected both comparators to the divider and to one ramp. Each comparator's OUT goes high while the ramp is outside the band between the taps, and falls as soon as the ramp comes back inside. In the finished timer the capacitor must keep charging after the trigger comparator's OUT falls, until it reaches 2/3 of the supply. So the timer needs one bit of memory that records which comparator was high last.

In Experiment 2 that memory was a latch made from two NOR gates in a CD4001B chip. A NOR gate's output is high only when both of its inputs are low. This experiment builds one NOR gate from two 2N3904 transistors and three resistors, and measures it. Experiment 11 builds the second gate and joins the two into the latch. Figure 10-1 shows where this gate goes.

Logic diagram of the latch from two NOR gates. Gate 1, labelled Q15 and Q16, this experiment, is drawn dark. Its upper input comes from a terminal on the left labelled threshold OUT, and its output leaves on the right as Q. Gate 2, labelled Q17 and Q18, Experiment 11, is drawn pale below it, with its lower input from a terminal labelled trigger OUT and its output labelled Q-bar. Two pale feedback wires cross between the gates: Q goes to Gate 2's upper input, and Q-bar goes to Gate 1's lower input. A small arc marks where the two wires cross without a connection.
Figure 10-1: The latch, with the gate that this experiment builds in colour. Experiment 11 adds the pale parts.

You will need

The switch from Experiment 3 is an inverter

The NOR gate starts from a circuit that this course built in Experiment 3: the transistor switch. One 2N3904 has a 10 kΩ resistor into its base, a 1 kΩ resistor from its collector to +5 V, and its emitter on ground. The collector is the output. Experiment 3 tested this switch as a comparator and found three flaws. Its output fell over a band of input from 0.60 V to 1.10 V. The transistor itself set where that band starts, and the band moved when the transistor became warm.

A logic circuit uses the same switch in a different way. In this course a 0 is a voltage near 0 V and a 1 is a voltage near +5 V, as in Experiment 2. A logic input sits at one of those two levels, and the band is far from both. Figure 10-2 shows the switch's output for every input from 0 V to 5 V. A 0 can rise by 0.6 V before the output starts to fall, and a 1 can drop by 3.9 V. In Experiment 3 a heat gun moved the band by 0.26 V, which is less than either of those.

Graph of the switch's output voltage against its input voltage, both from 0 to 5 volts. The output stays at 5 volts up to an input of 0.6 volts, falls steeply across a shaded band from 0.60 to 1.10 volts, labelled the fall, Experiment 3, and then stays close to 0 volts up to 5 volts of input. Three circles mark measured points: 5.00 volts out with 0 volts in, this experiment; 0.15 volts out with 2 volts in, Experiment 3; and 0.034 volts out with 5 volts in, this experiment. A green arrow from 0 to 0.6 volts of input is labelled 0.6 volts, room for a 0. A green arrow from 1.10 to 5 volts is labelled 3.9 volts, room for a 1.
Figure 10-2: The switch's output for every input from 0 V to 5 V. The circles are measured values, and the curve is drawn through them.

So a 0 at the input gives a 1 at the output, and a 1 gives a 0. A circuit that does this is an inverter, also called a NOT gate. The three flaws that matter in a comparator do not change the output of an inverter, because its input stays out of the band.

A second transistor makes a NOR gate

An inverter has one input, and each gate of the latch needs two. The second input gets its own transistor. Put a second 2N3904 beside the first, with its collector on the same collector line and its emitter on the same ground. Give it its own 10 kΩ and its own input. Figure 10-3 shows the result: Q15 takes input A, Q16 takes input B, and both share the 1 kΩ pull-up and OUT. The name pull-up says what the resistor does: it pulls OUT up to +5 V while neither transistor conducts.

Schematic of the NOR gate. A +5 volt symbol at the top feeds a 1 kilohm resistor down to a horizontal collector line. The collector line joins the collectors of two NPN transistors, Q15 on the left and Q16 on the right, and continues right to a terminal labelled OUT. Both emitters run down to one ground line with one ground symbol. Input A comes in from the left through a 10 kilohm resistor straight into Q15's base. Input B comes in from the left below it through a second 10 kilohm resistor, hops Q15's emitter wire, and rises into Q16's base.
Figure 10-3: The NOR gate. Each input reaches its own transistor through a 10 kΩ. The two collectors share OUT and the 1 kΩ pull-up.

Figure 10-4 draws the same circuit four times, once for each combination of the two inputs. A transistor that is off is pale, and green arrows show where current flows. The list gives the reason for each panel, in the same order.

Four copies of the NOR gate in a two by two grid. Top left: A equals 0, B equals 0, both transistors pale, OUT equals 1 at 5.00 volts. Top right: A equals 0, B equals 1, Q15 pale and Q16 dark, green arrows down through the 1 kilohm resistor, labelled 5 milliamps, and into Q16's collector, OUT equals 0 at 0.03 volts. Bottom left: A equals 1, B equals 0, Q15 dark and Q16 pale, arrows through the resistor and into Q15's collector, OUT equals 0 at 0.03 volts. Bottom right: A equals 1, B equals 1, both transistors dark, thinner arrows into both collectors, OUT equals 0 at 0.03 volts.
Figure 10-4: The four input combinations. Read the panels left to right, then top to bottom.
  1. A = 0, B = 0. No current flows into either base, so both transistors are off. No current flows through the 1 kΩ, so there is no voltage across it. OUT is at +5 V: a 1.
  2. A = 0, B = 1. Current flows into Q16's base through its 10 kΩ, and Q16 turns fully on. About 5 mA then flows from +5 V through the 1 kΩ and Q16 to ground. The 1 kΩ takes almost all of the 5 V, so OUT is near 0 V: a 0.
  3. A = 1, B = 0. The same happens with Q15 in place of Q16. OUT is a 0.
  4. A = 1, B = 1. Both transistors are on, and the 5 mA divides between them. OUT is a 0, at the same low level as with one input at 1.

So OUT is a 1 only when A and B are both 0. That is the NOR rule from Experiment 2. Without the inversion it would be the OR rule: high when A or B is high. Remove Q16, and the circuit is the inverter again.

Build the gate

The gate goes in the lower block, right of the trigger comparator, in columns 28 to 33. Its emitters go on the inner bottom rail, which is ground. So the transistors stand in row h with their flat faces towards the far edge, like Q12 to Q14. Each input is a 10 kΩ from its transistor's base down to the bottom rails. The rail that holds its lower leg sets the input. The inner bottom rail is ground, a 0, and the outer bottom rail is +5 V, a 1. Nothing crosses the centre channel, so the upper block above the gate stays empty. Experiment 11 puts the second gate there, straight above this one.

Experiment 9 left the generator, the crocodile-clip lead and two oscilloscope probes on the comparators, so those come off first. The two 1 kΩ ramp resistors in 13j and 20a stay. Figure 10-5 shows the finished gate and where the multimeter goes.

The breadboard drawn 40 columns wide, with both comparators, the divider, the tap jumpers and the two 1 kilohm ramp resistors faded. In colour, in the lower block: Q15, a 2N3904, at 28h to 30h and Q16 at 31h to 33h, both with their flat faces towards the far edge, labelled above the board. A green jumper joins 28i and 31i. Blue jumpers run from 30j on a short diagonal to the bottom ground rail at column 29, and from 33j straight down to the rail at column 33. A 1 kilohm pull-up stands from 31j over the ground rail to the outer bottom rail. A 10 kilohm leans from 29j down to the inner bottom rail at column 28, labelled input A: 10 kilohm, bottom rails: ground equals 0, +5 volts equals 1. A second 10 kilohm runs from 32j straight down to the inner bottom rail, labelled input B: the same. The upper block above the gate is empty. Rings mark the multimeter's red probe on OUT at 28j and its black probe on the bottom ground rail at column 37.
Figure 10-5: The NOR gate in columns 28 to 33, with both inputs at 0 and the multimeter on OUT. Click to enlarge.
  1. Switch off the 5 V supply and the generator.
  2. Remove the instrument connections of Experiment 9. Unclip the generator's red lead from the 1 kΩ in 20a. Leave its black lead on the top ground rail at column 7. Remove the crocodile-clip lead and both oscilloscope probes.
  3. Fit Q15. Put a 2N3904 in 28h, 29h and 30h, with its flat face towards the far edge. Its legs read collector, base, emitter from left to right.
  4. Fit Q16 in 31h, 32h and 33h, the same way round.
  5. Join the collectors. Fit a jumper from 28i to 31i.
  6. Connect Q15's emitter to ground. Fit a jumper from 30j to the inner bottom rail at column 29. The rail has no hole at column 30.
  7. Connect Q16's emitter to ground. Fit a jumper from 33j to the inner bottom rail at column 33.
  8. Fit the 1 kΩ pull-up from 31j to the bottom +5 V rail, the outer one. It reaches over the ground rail.
  9. Fit the 10 kΩ for input A from 29j to the inner bottom rail, the ground one, at column 28. Column 29 of that rail holds Q15's emitter jumper. This sets A to 0.
  10. Fit the 10 kΩ for input B from 32j to the inner bottom rail at column 32. This sets B to 0.

Always set an input through its 10 kΩ. A wire from +5 V straight to a base puts the base-emitter junction directly across the supply. The supply then reaches its 50 mA current limit, the +5 V rail falls for the whole board, and the transistor can be damaged.

Measure the four combinations

The gate is complete, with both inputs at 0. The multimeter now reads OUT for each combination of Figure 10-4. Expect about 5.00 V for the first combination and a few hundredths of a volt for the other three.

  1. Switch on the 5 V supply. The generator stays off.
  2. Measure OUT with A = 0 and B = 0. Put the multimeter's black probe on the bottom ground rail at column 37 and its red probe on 28j. Expect about 5.00 V.
  3. Set A to 1. Move the lower leg of A's 10 kΩ from the inner bottom rail to the outer bottom rail, the +5 V one. Expect about 0.03 V.
  4. Set A to 0 and B to 1. Move A's leg back to the inner bottom rail. Move the lower leg of B's 10 kΩ to the outer bottom rail. Expect about 0.03 V.
  5. Set A to 1 as well. Move A's leg to the outer bottom rail. Expect about 0.03 V.
  6. Set both inputs back to 0. Move both legs to the inner bottom rail.

If OUT stays near 0 V with both inputs at 0, check the input resistors. The lower leg of each must be in the inner bottom rail. Also check that each transistor has its flat face towards the far edge. If OUT stays near 5 V with an input at 1, check that the pull-up goes to the outer bottom rail. Both emitter jumpers must go to the inner bottom rail.

The table gives the expected values, the readings from my first build of this gate, and two readings from my current board. Figures 10-6 and 10-7 show the multimeter for these two readings.

ABOnOUTExpectedMy first buildMy current board
00neither15.00 V5.001 V5.003 V
01Q1600.03 V0.034 Vnot measured
10Q1500.03 V0.034 V0.050 V
11both00.03 V0.034 Vnot measured
A Brymen BM235 multimeter reading 5.003 volts. Its probes are on the output of the NOR gate on my current board, with both inputs at 0.
Figure 10-6: OUT with both inputs at 0 on my current board: 5.003 V.
A Brymen BM235 multimeter reading 0.050 volts. Its probes are on the output of the NOR gate on my current board, with input A at 1 and input B at 0.
Figure 10-7: OUT with A at 1 and B at 0 on my current board: 0.050 V.

OUT is a 1 only with both inputs at 0, so the gate follows the NOR rule. The 1 is within a few millivolts of 5 V on both boards: with both transistors off, almost no current flows through the 1 kΩ. On my first build the 0 read 0.034 V in all three combinations with an input at 1. On my current board it read 0.050 V with A at 1. Both are lower than the 0.15 V that Experiment 3 measured on the same switch, and the next section explains the difference.

Why the low is 0.034 V

A transistor that is fully on is saturated, as Experiment 3 described. Its low level depends on how much base current it gets, compared with the base current that its collector current needs.

  1. With an input at 5 V, the base sits about 0.7 V above ground. So the 10 kΩ has about 4.3 V across it, and drives 4.3 V / 10 kΩ = 0.43 mA into the base.
  2. The 1 kΩ lets at most 5 V / 1 kΩ = 5 mA flow into the collector.
  3. The 2N3904 datasheet gives a current gain of at least 70 at 1 mA and at least 100 at 10 mA. So 5 mA of collector current needs at most about 5 mA / 70 = 0.07 mA of base current.
  4. The 10 kΩ supplies about six times that base current. The extra base current pushes the transistor further into saturation, and the low comes closer to 0 V.

Experiment 3 drove the same switch from a 2 V input. That gave (2.0 V − 0.7 V) / 10 kΩ = 0.13 mA of base current and a low of 0.15 V. The gate's 5 V input gives more than three times that base current, and the low falls to 0.034 V. A low this close to 0 V is useful in Experiment 11, where the OUT of one gate drives an input of the other. Figure 10-2 shows that a 0 at 0.034 V is far below the 0.6 V where the next transistor starts to conduct.

Why more base current gives a lower low

The list under “Why the low is 0.034 V” said that extra base current pushes the transistor further into saturation. Here is what happens inside it. A transistor is saturated when both of its junctions conduct: base to emitter, and base to collector. The collector-to-emitter voltage is then the difference between the two junction voltages:

With barely enough base current, the base-collector junction conducts only a little. Its voltage is well below the base-emitter voltage, and the difference is a few tenths of a volt. More base current makes the base-collector junction conduct harder, and its voltage comes closer to the base-emitter voltage. The difference then shrinks to a few tens of millivolts. With both inputs at 1, each transistor gets the same base current and carries only part of the 5 mA. So each one is at least as far into saturation as a single transistor, and the low cannot rise. On my first build it read 0.034 V in all three combinations.

Watch the gate invert

The multimeter showed the four combinations one at a time. The oscilloscope shows the gate following an input that changes. The generator drives input A with a square wave from 0 V to 5 V, and input B stays at 0. Figure 10-8 shows the connections. Oscilloscope channel 1 still shows the generator's signal through the BNC T-piece, as in Experiment 9.

The breadboard with everything from Figure 10-5 faded, including input B's 10 kilohm in the bottom ground rail. Input A's 10 kilohm stands in 29j with its lower leg out of the rail, leaning down and left. Rings mark the generator's red lead on that free leg, labelled input A: generator red lead, square 0 to 5 volts, 100 hertz; the oscilloscope channel 2 tip on OUT at 31f; and the channel 2 ground on the bottom ground rail at column 37. A faded ring marks the generator's black lead on the top ground rail at column 7.
Figure 10-8: The generator on input A and oscilloscope channel 2 on OUT. Input B stays at 0. Click to enlarge.
  1. Switch off the 5 V supply.
  2. Free A's 10 kΩ. Pull its lower leg out of the bottom rail, and bend it so that the free leg stands over the bottom rails. Its upper leg stays in 29j.
  3. Set the generator to a square wave at 100 Hz with a high level of 5 V and a low level of 0 V. Keep its load setting at HiZ.
  4. Connect the generator. Clip its red lead onto the free leg of A's 10 kΩ. Its black lead stays on the top ground rail at column 7.
  5. Connect the probe. Put the oscilloscope channel 2 tip on 31f and its ground clip on the bottom ground rail at column 37.
  6. Set the oscilloscope: channels 1 and 2 at 1 V/div, and the timebase at 2 ms/div. Put the ground markers of both channels at the same height, near the bottom of the screen. Switch channel 3 off. Trigger on channel 1, rising, at 2.5 V.
  7. Switch on the 5 V supply and the generator.
Oscilloscope with channels 1 and 2 at 1 volt per division and the same ground marker, 2 milliseconds per division, triggered on channel 1 rising. The yellow trace, input A, is a square wave from 0 to 5 volts at 100 hertz. The magenta trace, OUT at 31f, is the mirror image of A: near 5 volts while A is near 0 volts, and near 0 volts while A is near 5 volts. Both traces are thin.
Figure 10-9: Input A in yellow and OUT in magenta, with input B at 0.

With B at 0, the gate is an inverter: OUT is high while A is low, and low while A is high. Now set B to 1 while A keeps switching.

  1. Set B to 1. Move the lower leg of B's 10 kΩ to the outer bottom rail. Expect OUT to stay near 0 V.
  2. Set B back to 0. Move the leg back to the inner bottom rail.
  3. Switch off the generator and the 5 V supply.

With B at 1, OUT stays low and the square wave on A has no effect. One input at 1 is enough to hold OUT low, whatever the other input does. That is the OR in the NOR rule.

This gate flew to the Moon

NOR gates alone can make any logic function: NOT, OR, AND, and also memory. The Apollo Guidance Computer, which steered the Apollo spacecraft to the Moon, used that fact. It was one of the first computers made from integrated circuits. The version that flew used about 2,800 identical chips, each with two three-input NOR gates. Each of those gates had the form of Figure 10-3 with a third transistor. This kind of logic is called resistor-transistor logic, often shortened to RTL.

RTL has two weak points. A saturated transistor takes time to turn off, because its base has to lose the extra charge that saturation put there. And the 1 comes only through a pull-up resistor, so one output can drive only a few inputs. Later logic families, first TTL and then CMOS, replaced RTL for those reasons. Neither weak point matters in this timer. Its latch changes state at the speed of a charging capacitor, and each gate output drives only a few inputs.

Quick check

Three questions on this experiment. They ask when OUT is high, what happens with both inputs at 1, and why the switch's flaws from Experiment 3 do not matter in a gate.

1. OUT is near +5 V only when…

The pull-up holds OUT at +5 V only while no current flows through it. That needs both transistors off, so both inputs at 0. One input at 1 turns its transistor on, and OUT falls to a few hundredths of a volt.

2. With both inputs at 1, OUT…

One saturated transistor already holds OUT a few tens of millivolts above ground. A second one in parallel shares the current and cannot take OUT below ground. My first build read 0.034 V for one input at 1 and for both.

3. The switch from Experiment 3 has a wide transition that moves with temperature. In a gate this does not change the output, because…

The output falls only for inputs between about 0.60 V and 1.10 V. A 0 has 0.6 V of room below that band and a 1 has 3.9 V above it. The heat gun moved the band by 0.26 V, which is less than either.

Before moving on

Two transistors, a shared 1 kΩ pull-up and two 10 kΩ resistors make a NOR gate. Its 1 is 5.00 V and its 0 is 0.034 V, both far from the band where the switch changes state. The gate stays on the board, in columns 28 to 33.

The gate still remembers nothing: OUT follows its inputs at every moment. Experiment 11: The SR Latch builds a second gate above this one and connects each gate's OUT to an input of the other. The pair then keeps its state after the input that set it returns to 0.

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