Full Stack Electronics · Stage Four · Experiment 18

Experiment 18: The Board

The fifth step from the breadboard to a printed circuit board. Draw the outline, place the 51 footprints as seven blocks, route the tracks and pour the ground, until the design rules checker finds nothing to report.

Experiment 17 gave each of the 51 symbols a footprint. The footprints have sizes, but no positions, and no copper connects them. The layout gives the board an outline, puts each footprint at its place, and draws copper for each connection of the netlist. The schematic cannot show the things that the layout decides: which parts sit side by side, how long each connection is, and where the ground current flows back. This experiment makes the layout of the board of this course in KiCad's PCB Editor. The board has the shape of an NE555, with the eight pins of the chip at its edges. So it can take the place of the chip on the breadboard of Experiment 1. The result is the board of Figure 18-1, and a check by the design rules checker that reports zero errors and zero connections that are not routed.

From the schematic to the PCB Editor

Figure 18-1 is the end of this experiment. The start is a board file with no outline and no footprints. The PCB Editor gets the footprints and the netlist from the schematic.

1. Open the PCB Editor. In the Project Manager of the master project, double-click 555.kicad_pcb. If the file does not exist yet, KiCad makes it.
2. Get the footprints. Select Tools → Update PCB from Schematic, or press F8. The window lists the changes, one line for each footprint. Click Update PCB. The 51 footprints arrive in a group, and you place the group with a click.
3. Look at the ratsnest. A thin line joins each pad to the next pad on the same net. These lines are the ratsnest: the connections that the netlist asks for and that no copper makes yet. This board has 126 pads on 31 nets, so it needs 95 connections. Each track that you draw removes one line.

The outline and the eight pins

The ratsnest shows what to connect. Before the parts can go anywhere, the board needs its outline. This board has the shape of the chip that it replaces. Its pins are J1, at the edges, in the order of the NE555: pin 1 at the top left next to the notch, then anticlockwise, as Experiment 1 counted them. Eight jumper leads connect each pin to the row of the breadboard where the same pin of the NE555 sat. The rest of the circuit of Experiment 1 stays as it is.

1. Draw the outline. Select the layer Edge.Cuts. Draw a rectangle 46 mm wide and 56 mm high, with corners of 2 mm radius. Cut a half circle of 2.5 mm radius into the middle of the top edge, as the notch of a chip. The outline must be one closed shape. KiCad shades the area inside a closed outline, so the shade shows that the outline is closed.
2. Move the pads of J1. The footprint of Experiment 17 puts the eight pads in one row, 2.54 mm apart. Double-click J1, click Edit Footprint…, and move the pads in the Footprint Editor. Pads 1 to 4 go down the left side and pads 5 to 8 up the right side, 41 mm apart, with 12.7 mm between pins. Save the footprint, and the Footprint Editor writes it back to the board. This changes only J1 on this board. The library footprint stays the same.
3. Place J1. Put pad 1 at the top left, 2.5 mm in from the edge, and pad 8 at the top right. The top pads then sit 9.0 mm below the top edge, and the bottom pads 8.9 mm above the bottom edge.

The netlist connects each net to a pad number, so the new positions of the pads change nothing in the schematic. Pad 1 is square, so the board shows pin 1 as a chip does.

Board Setup

With the outline in place, set the rules for the copper before you route. KiCad uses these rules while you draw tracks, and the design rules checker tests the board against them. Select File → Board Setup…. The table gives the values of this board. None of them asks more than the usual process of a board factory.

A net class is a set of nets with the same track width and via size. In the lower part of the section Net Classes, assign the patterns +5V and GND to the class Power. Then KiCad draws each supply track 0.508 mm wide and each signal track 0.254 mm wide, with no further setting. The values are 10 and 20 thousandths of an inch. If a field shows an odd value such as 3.937, its unit is a thousandth of an inch: 3.937 is 0.1 mm. Type the unit with the value, as in 0.2mm, and KiCad converts it.

Place the blocks

The rules are set, and the 51 footprints are still a group beside the outline. Do not place them one by one. The board is the seven blocks that Stage Three built: the two comparators, the divider, the latch, the output stage, the discharge transistor and the reset block. Most of the connections stay inside one block. Figure 18-2 shows where each block sits on this board.

Only six signal nets join two blocks or more. The table gives them, with the blocks that each one joins. Apart from +5 V and GND, five of them have the longest tracks of the board, from 76 mm for Q̄ to 38 mm for Q. REF13 has 21 mm, because the divider sits next to the trigger comparator. So the blocks that share a net sit next to each other where they can.

The two comparators take an input from the divider, so the three sit side by side at the top. The latch sits under them, at the bottom right, and the reset block beside it, because Q and S run between the two. The output and discharge transistors sit in the middle row, next to their pins: Q19 near OUT on the left, Q20 near DIS on the right. C1 sits beside pin 8, where +5 V comes onto the board.

1. Put the blocks in their areas. Right-click a transistor of a comparator and select Select → Items in Same Hierarchical Sheet. KiCad selects the whole sheet, as Experiment 15 drew it. Press P to pack the selection and move it to its area of Figure 18-2. Do the same for the latch and the reset block. The divider, Q19, Q20, R14, R15, R21, C1 and the test pads are all on the root sheet, so move them one by one.
2. Put each pair side by side. Experiment 4 kept the two transistors of a pair close together, so that they are at one temperature. On the board, each pair of a comparator sits side by side, the same way round. In the threshold comparator the pairs are Q1 and Q2, Q3 and Q4, and Q5 and Q6. In the trigger comparator they are Q8 and Q9, Q10 and Q11, and Q12 and Q13.
3. Make the ratsnest short. Move and turn the parts in each block, with R to turn, until the ratsnest lines are short and cross as little as possible. A crossing that you remove now is a via that you do not need later.
4. Put the test pads in a row. TP1 to TP4, on S, R, Q and Q̄, go in one row in the middle of the board, with their names on the silkscreen. TP5, on REF13, sits above the row. The test pads are for the probe of an oscilloscope in Experiment 21.
5. Draw the boxes. On the layer F.Silkscreen, draw a box around each block and write its name. Then the board shows its own block diagram.

Route the tracks

With each part in its place, the ratsnest is short, and each line becomes a track. Route inside each block first, then the six nets between the blocks, then the pins.

1. Route a track. Press X, click a pad, and click along the path to the other pad. The track takes the width of its net class. Its ratsnest line goes when the track reaches the pad.
2. Change sides with a via. If a track must cross another, press V while you route. KiCad puts a via, a plated hole between the two copper layers, and the track continues on the back. On this board most tracks are on the front.
3. Route +5 V. Route +5 V from pin 8 along the top of the board into each block. It is 0.508 mm wide from its net class.
4. Leave GND. Do not route GND as tracks. The next section gives the ground a whole layer.

Pour the ground

Figure 18-3 has no ground track. The ground is one sheet of copper on the back of the board, a zone. Each ground pad on the front connects to it through a via next to the pad. A sheet gives each ground connection a short and wide path to each other one. On a breadboard, the ground return went through the rails and the jumper wires.

1. Draw the zone. Select the layer B.Cu and the tool Add Filled Zone, or press Ctrl+Shift+Z. In the Zone Properties window, select the net GND. Click the corners of a shape a little larger than the board, and double-click to close it. The copper fills only inside the outline.
2. Connect the ground pads. Connect each ground pad on the front to the zone through a via, next to the pad or at the end of a short track. Pads close together can share one via. On this board, 14 vias connect the 18 ground pads of the front to the zone. Pad 1 of J1 goes through the board, so the zone connects to it directly.
3. Fill the zone. Press B. KiCad fills the zone around each track, pad and via of another net, with its clearance of 0.5 mm. A zone does not fill again by itself. After each change near it, press B again.
4. Look at the back. The back must be one sheet with few holes in it. If tracks on the back cut it into separate parts, move the tracks to the front, or move parts until the sheet joins again.

Check the board

The zone is full, and the board has all its copper. The design rules checker now tests the copper against the rules of Board Setup and against the schematic.

1. Run the checker. Select Inspect → Design Rules Checker. Select Refill all zones before performing DRC and Test for parity between PCB and schematic. Click Run DRC.
2. Read the three tabs. Violations lists the copper that breaks a rule. Unconnected Items lists the ratsnest lines that are left. Schematic Parity lists differences between the board and the schematic. The aim is zero in each tab.
3. Correct each item. Click an item to see it on the board. Correct it, run the checker again, and continue until each tab is empty.

The first full check of this board, after I routed it by hand, did not give zero. The tab Unconnected Items was empty, but the tab Violations had three errors. A track of RST, the collector net of Q21, landed on the wrong pad of R20 and shorted the resistor, so Q23 would have had no base resistor. Two ground vias were too close to the collector pads of transistors. One short track ended on nothing. A zone that I had not filled again after the last tracks also gave 58 clearance violations, and those went with B. The short across R20 is the important one. The timer would run with it, because the timer does not use the reset, so the fault would show only at the first reset of the board.

After the corrections, the board of this course gives 0 violations, 0 unconnected items and 0 parity issues. Its Board Setup sets some checks to ignore. With those checks on, the checker gives one warning: “Footprint 'PinHeader_1x08_P2.54mm_Vertical' does not match copy in library 'Connector_PinHeader_2.54mm'”, on J1. That is correct, because the pads of J1 moved. If your checker gives this warning, right-click it and select Exclude with comment…, with a comment such as “pads moved to the edges”. Then the checker shows the exclusion with its reason, and it continues to compare the footprints of all the other parts with the library.

Before moving on

The board has its outline, its 51 footprints in seven blocks, 269 track segments, 31 vias and a ground zone on the back. The design rules checker reports 0 violations, 0 unconnected items and 0 parity issues, apart from the expected warning for J1. That is the fifth step from the breadboard to the board. Experiment 19: Before You Order checks the board in the ways that the checker cannot, writes the files for the factory and orders the board.