Full Stack Electronics · Stage Three · Experiment 13

Experiment 13: The Reset Pin

Add three transistors for pin 4 of the NE555. A low on RESET stops the timer and empties the capacitor, and the next cycle starts from 0 V.

Experiment 12 closed the loop, and the board runs as a 555 astable. Nothing outside the board can stop it. The NE555 has one more input for that: pin 4, RESET. In Experiment 1, pin 4 went to +5 V, so the reset stayed off. The TI datasheet for the NE555 gives the rule in its function table. While RESET is low, the output is low and the discharge transistor is on. TRIGGER and THRESHOLD then have no effect. The datasheet also says that RESET is used to start a new timing cycle.

On this board a low on RESET must do two things. It must hold Q at 0, so that Q19 turns the LED off. It must also hold DIS at 0 V, so that C empties. This experiment adds the reset block, three transistors Q21 to Q23, and a fifth lead for the 555's pins, RESET. Q21 and Q22 go in first, and the oscilloscope shows what they do not do. Q23 then completes the reset.

You will need

An inverter and a third input for Gate 1

RESET is active low: it acts when it is 0. A transistor switch acts when its base gets a 1. So the reset block starts with an inverter, Q21, the transistor switch of Experiment 3. Figure 13-1 shows Q21 and the first transistor that it drives, Q22.

Schematic with one +5 volt line along the top and one ground line along the bottom. Input RESET comes in from the left through a 10 kilohm resistor to the base of Q21. A 10 kilohm resistor runs from the +5 volt line down to Q21's collector, a node labelled RST. From RST a wire goes down through a second 10 kilohm resistor to the base of Q22. Q22's collector rises to a wire that runs right to a terminal labelled Q. Both emitters go to the ground line.
Figure 13-1: Q21, the inverter, and Q22, which holds Q at 0 during a reset.
  1. RESET is at +5 V. Current flows through Q21's 10 kΩ into its base, so Q21 is on and holds its collector near 0 V. Call that collector RST.
  2. RST is near 0 V, so Q22 gets no base current and is off. The timer runs as in Experiment 12.
  3. RESET goes to 0 V. Q21 turns off, and its 10 kΩ pull-up lifts RST. Current flows from RST into Q22's base, and Q22 turns on.
  4. Q22's collector is on Q, the output of Gate 1. Q22 holds Q at 0, as Q15 and Q16 do. Q19 turns off, and the LED goes off.

Q22 is a third transistor on Gate 1's pull-up. Gate 1 is now a NOR gate with three inputs: R, Q̄ and RST. A 1 on any input makes Q 0, as in the NOR gate of Experiment 10.

Is the base current enough?

Q22 must hold Q at 0 against Gate 1's 1 kΩ pull-up.

  1. With Q21 off, current flows from +5 V through the pull-up and Q22's 10 kΩ into Q22's base, which sits about 0.7 V above ground. So the base current is (5 V − 0.7 V) / 20 kΩ = 0.22 mA.
  2. With Q near 0 V, the pull-up puts about 5 V / 1 kΩ = 5 mA into Q22's collector.
  3. So Q22 needs a current gain of 5 mA / 0.22 mA, about 23. The onsemi datasheet for the 2N3904 gives at least 100 at 10 mA, so Q22 holds Q near 0 V.

Build Q21 and Q22

Q21 and Q22 are inside a 555, so they go next to Q19 and Q20. Experiment 12 left columns 41 to 49 free for them, between Q19 and the LED. Q21 and Q22 stand one above the other in columns 43 to 45, two columns right of Q19 and Q20, as Q19 and Q20 stand two columns right of the latch. Q21 faces the same way as Q20, and Q22 the same way as Q19. Q21's base resistor runs back into the two columns between, to column 41. A resistor needs its legs at least three columns apart, because its body is longer than two hole spacings. A 10 kΩ diagonally across the centre channel takes RST from Q21's collector to Q22's base, and a wire along row f takes Q to Q22's collector. Figure 13-2 shows the new parts.

The breadboard with everything from Experiments 3 to 12 faded. In colour, one above the other in columns 43 to 45, two columns right of Q19 and Q20. In the upper block: Q21, a 2N3904, at 43d to 45d with its flat face towards the near edge, as Q20, and a blue jumper from 43a to the outer top rail. A 10 kilohm resistor from 45a to the inner top rail, labelled 10 kilohm pull-up. A 10 kilohm resistor along row b from 44b to 41b, labelled 10 kilohms for Q21's base. In the lower block: Q22, a 2N3904, at 43h to 45h with its flat face towards the far edge, as Q19, and a blue jumper from 45j to the inner bottom rail. A 10 kilohm resistor diagonally across the centre channel from 45e to 44f, labelled 10 kilohms for Q22's base. A yellow wire along row f from 37f to 43f, labelled Q wire.
Figure 13-2: Q21 above Q22, inside the 555, two columns right of Q20 and Q19. Click to enlarge.
  1. Switch off the 5 V supply. Remove both oscilloscope probes.
  2. Fit Q21. Put a 2N3904 in 43d, 44d and 45d, with its flat face towards the near edge, as Q20. Its legs read emitter, base, collector from left to right.
  3. Connect Q21's emitter to ground. Fit a jumper from 43a to the outer top rail at column 43. It crosses over the inner rail.
  4. Fit Q21's pull-up. Fit a 10 kΩ from 45a to the inner top rail at column 45, the +5 V one. The upper strip of column 45 is RST.
  5. Fit Q21's base resistor. Fit a 10 kΩ along row b, from 44b to 41b. The upper strip of column 41 is RESET.
  6. Fit Q22 below Q21. Put a 2N3904 in 43h, 44h and 45h, with its flat face towards the far edge, as Q19. Its legs read collector, base, emitter from left to right.
  7. Connect Q22's emitter to ground. Fit a jumper from 45j to the inner bottom rail at column 45.
  8. Fit Q22's base resistor. Fit a 10 kΩ diagonally across the centre channel, from 45e to 44f. It takes RST to Q22's base.
  9. Connect Q. Fit a wire along row f from 37f to 43f. The lower strip of column 37 is Q: it holds the end of the Q wire and the left leg of Q19's base resistor.

The RESET lead

RESET is a pin of the 555, so a lead connects it to the outside, as for OUT, DIS, TRG and THR. In Experiment 1, pin 4 went to +5 V. The RESET lead does the same here. For a reset, its end moves to the ground rail next to it. Figure 13-3 shows both positions.

The breadboard with everything faded except one cyan lead tagged RESET. It goes from 41a over the top of the board and down into the inner top rail at column 46. A cyan ring on the outer top rail at column 44 is labelled for a reset: the lead's end here.
Figure 13-3: The RESET lead in the +5 V rail. For a reset, its end goes in the ground rail at the ring. Click to enlarge.
  1. Fit the RESET lead from 41a to the inner top rail at column 46, the +5 V one.
  2. Switch on the 5 V supply. The LED blinks as before, because RESET at +5 V keeps Q21 on and Q22 off.

If the LED stays dark, RST is not near 0 V and Q22 holds Q at 0. Switch off, and check that the RESET lead is in the +5 V rail. Then check Q21, its emitter jumper and its base resistor.

Keep the lead's end in a rail. With the end loose, no current flows into Q21's base. Q21 is then off, and the board stays in reset. A loose lead can also pick up noise. The NE555 datasheet gives the same rule: to prevent false triggering, connect RESET to VCC when it is not used.

Look at a reset

A reset happens between two moves of the lead, so the oscilloscope must catch it on one sweep. Channel 3 shows RESET and triggers the sweep when RESET rises again. Channels 1 and 2 stay on OUT and CAP, as in Experiment 12.

Oscilloscope channelTip or hookGround clip
Channel 1: OUT50h, the LED's cathodeInner bottom rail, column 51
Channel 2: CAP54h, C's positive leadInner bottom rail, column 53
Channel 3: RESET41d, the strip of the RESET leadInner bottom rail, column 41
The board faded, leads included. A yellow ring on 50h is labelled OUT: channel 1 tip. A magenta ring on 54h is labelled CAP: channel 2 tip. A cyan ring on 41d is labelled RESET: channel 3 tip. Blue rings on the inner bottom rail at columns 51, 53 and 41 are labelled channel 1 ground, channel 2 ground and channel 3 ground.
Figure 13-4: Oscilloscope channel 1 on OUT, channel 2 on CAP and channel 3 on RESET. Click to enlarge.
  1. Switch off the 5 V supply. Connect the three probes as the table shows.
  2. Match the probe settings. Set the switch on each probe to 10×, and set Probe to 10X for CH1, CH2 and CH3.
  3. Set the scales. Channels 1 and 2 at 1 V/div, with both ground markers near the bottom of the screen, as in Experiment 12. Channel 3 at 5 V/div, with its ground marker two divisions above the centre. All three DC coupling. Timebase 100 ms/div.
  4. Set the trigger: Edge, source CH3, rising slope, level 2.5 V, mode Normal. Keep the trigger point at the centre of the screen. The left half of the screen then shows the reset, and the right half shows the restart.
  5. Switch on the 5 V supply. The LED blinks.
  6. Reset the timer. Move the RESET lead's end to the outer top rail at column 44. After about half a second, move it back to the inner rail at column 46. The rising edge on RESET starts the sweep, and the screen holds it.

While RESET is low, OUT is high and the LED is dark. That part works. Now look at CAP. At the start of the reset it falls, as in a normal discharge. Then it stops at the lower turning point and stays there until RESET rises. In Figure 13-5 the reset lasted longer than the left half of the screen, so CAP is already flat at the left edge, at 1.68 V. After the release the LED lights, and the first charge starts from that level and ends at the upper turning point, 3.30 V.

Oscilloscope at 100 milliseconds per division, triggered on channel 3 rising at 2.5 volts with the trigger point at the centre. Channels 1 and 2 at 1 volt per division with the same ground marker near the bottom, channel 3 at 5 volts per division with its ground marker two divisions above the centre. Left half: the cyan trace, RESET, is at 0 volts, the yellow trace, OUT, is high at about 3.7 volts, and the magenta trace, CAP, is flat at cursor Y1, 1.68 volts. At the centre RESET rises to 5 volts. Right half: OUT goes low and CAP rises in a curve to cursor Y2, 3.30 volts, then falls back to about 1.7 volts while OUT is high, three times. The cursor readout shows delta Y 1.62 volts, Y2 3.30 volts and Y1 1.68 volts.
Figure 13-5: A reset with Q21 and Q22. While RESET (cyan) is low, OUT (yellow) is high and the LED is dark, but CAP (magenta) stays at the lower turning point, 1.68 V. After the release the timer runs again from that level.

Why C stops at the lower turning point

The datasheet asks for the discharge transistor on during a reset. On the board, C stops near 1/3 of the supply, so Q20 does not stay on. Q22 holds Q at 0, but Gate 2 still has its other input, S. With Q at 0, Gate 2 is an inverter for S, and the trigger comparator continues its work. Follow Figure 13-6 through the loop that remains.

The loop of Figure 12-1, with the threshold comparator's side, Q19, the LED and its 220 ohm faded. A green pill on the Q wire reads Q22 holds Q at 0. In colour: the trigger comparator's output S into the latch, Q-bar through a 10 kilohm resistor to Q20's base, Q20's collector to DIS, RA from the +5 volt line to DIS, RB from DIS to C, and the TRG wire from C back to the trigger comparator. Green numbered markers: 1 beside Q20, 2 on the S wire, 3 below the Q-bar wire, 4 beside RA and RB.
Figure 13-6: The loop that holds CAP near 1/3 while Q22 holds Q at 0. The numbers match the steps below.
  1. Q̄ is 1, so Q20 is on. C discharges through RB into Q20, and CAP falls.
  2. CAP falls below 1/3 of the supply. The trigger comparator's OUT rises, so S is 1.
  3. S makes Q̄ 0, and Q20 turns off.
  4. C charges through RA and RB, and CAP rises above 1/3. S returns to 0, Q̄ returns to 1, and step 1 starts again.

Q20 discharges C only while CAP is above 1/3. So CAP stays near the lower turning point for as long as RESET is low. After the release, the first charge starts from that level, as every charge does. The timer continues as if the reset had not happened, and the datasheet's new timing cycle does not start.

Q20 takes its signal from the latch, and S can change the latch during a reset. So the reset needs a transistor on DIS that the latch does not control. Q23 is that transistor. Its collector goes to DIS, beside Q20's collector, and its base takes RST, as Q22's base does. Figure 13-7 adds it.

The schematic of Figure 13-1 faded, with new parts in colour. From the RST node a wire runs right, hops Q22's collector wire, and goes down through a 10 kilohm resistor to the base of Q23. Q23's collector rises to a wire that runs right to a terminal labelled DIS. Q23's emitter goes to the ground line.
Figure 13-7: Q23 holds DIS at 0 V during a reset. It takes RST and nothing from the latch.
  1. RESET goes to 0 V. Q21 turns off, RST rises, and both Q22 and Q23 turn on.
  2. Q22 holds Q at 0, so the LED is dark. Q23 holds DIS near 0 V, so C discharges through RB into Q23.
  3. CAP falls below 1/3, and S rises to 1. S makes Q̄ 0, and Q20 turns off. Q23 stays on, so C continues to discharge until CAP is near 0 V.

During the reset both latch outputs are 0: Q22 holds Q, and S holds Q̄. Experiment 11 found the same state with S and R both at 1, and here RST takes the place of R. It does no harm, because Q19 and Q20 are both off and Q23 alone holds DIS. Experiment 11 also found that the next state depends on the input that returns to 0 last. When RESET rises, RST returns to 0 and S is still 1, so S sets the latch. Q rises, the LED lights, and C charges from 0 V.

RST now drives two bases. The pull-up and the two 10 kΩ base resistors give (5 V − 0.7 V) / 15 kΩ = 0.29 mA, so each base gets 0.14 mA. Q22's 5 mA then needs a current gain of about 35, still far below 100. Q23 takes RA's 0.5 mA and the current from C, less than 1 mA in total.

Build Q23

Q23 goes in the upper block, in columns 47 to 49, and faces the same way as Q20 and Q21. Its base resistor runs along row b from the upper strip of column 45, RST. A yellow wire along row e joins its collector to DIS. Figure 13-8 shows the new parts.

The breadboard with everything faded except Q23 and two connections. Q23, a 2N3904, is at 47d to 49d with its flat face towards the near edge, labelled Q23: 2N3904. A blue jumper runs from 47a to the outer top rail. A 10 kilohm resistor runs along row b from 45b to 48b, labelled 10 kilohms for Q23's base. Its left end is in the strip of Q21's collector. A yellow wire along row e from 40e to 49e, over the top end of Q22's base resistor, is labelled DIS wire.
Figure 13-8: Q23 in the upper block, in columns 47 to 49. Click to enlarge.
  1. Switch off the 5 V supply.
  2. Fit Q23. Put a 2N3904 in 47d, 48d and 49d, with its flat face towards the near edge, as Q20 and Q21. Its legs read emitter, base, collector from left to right.
  3. Connect Q23's emitter to ground. Fit a jumper from 47a to the outer top rail at column 47.
  4. Fit Q23's base resistor. Fit a 10 kΩ along row b, from 45b to 48b. The upper strip of column 45 is RST.
  5. Connect DIS. Fit a wire along row e from 40e to 49e. It lies over the top end of Q22's base resistor in 45e. The upper strip of column 40 is Q20's collector, DIS, and the upper strip of column 49 is Q23's collector.

Look at the reset again

Keep the oscilloscope as it is. Switch on the 5 V supply, and reset the timer as before: the lead's end in the outer top rail at column 44 for about half a second, then back in the inner rail.

While RESET is low, OUT is high and the LED is dark, as before. CAP now falls past the lower turning point and continues down to near 0 V. After the release the LED lights at once, because CAP is below 1/3 and S sets the latch. The first charge then starts from near 0 V, so the LED stays on for longer than in each later cycle. By calculation the first charge takes about 220 ms, and each later charge 139 ms. The box “Where the 220 ms comes from” calculates the first one. In Figure 13-9 the cursors measure the first charge, from the release to the first rise of OUT: 210 ms. Each later charge is about 1.3 divisions, 130 ms, as in Experiment 12. The ratio of the two is 1.6 on the board and 220 ms / 139 ms = 1.6 by calculation.

Oscilloscope at 100 milliseconds per division, triggered on channel 3 rising at 2.5 volts with the trigger point at the centre, channels set as in Figure 13-5. Left half: the cyan trace, RESET, is at 0 volts, the yellow trace, OUT, is high at about 3.7 volts, and the magenta trace, CAP, is flat at 0 volts. At the centre RESET rises to 5 volts. Right half: OUT goes low and CAP rises in a curve from 0 volts to about 3.3 volts, then the timer runs normally: three shorter charges follow. Two vertical cursors on channel 1, X1 at the release and X2 at the first rise of OUT, read delta X 210 milliseconds.
Figure 13-9: A reset with Q23 fitted. While RESET (cyan) is low, OUT (yellow) is high and CAP (magenta) is at 0 V. After the release the first charge starts from 0 V and takes 210 ms between the cursors. The later charges are shorter.

If CAP still stops near the lower turning point, Q23 does not hold DIS. Switch off, and check Q23, its emitter jumper, its base resistor and the DIS wire along row e. If CAP stays near 0 V after the release, RST did not fall again: check that the RESET lead is back in the +5 V rail.

Where the 220 ms comes from

During a charge CAP moves towards 5 V through RA + RB, and the gap between the supply and CAP gets smaller. A normal charge starts with a gap of 2/3 of the supply and ends with a gap of 1/3, so the gap halves. That takes 0.69 RC, as Experiment 12 calculated: 139 ms.

The first charge after a reset starts with CAP at 0 V, so the gap is the full supply. It ends at the upper turning point, where the gap is 1/3 of the supply. So the gap falls to one third. That takes 1.10 RC: 1.10 × 20 kΩ × 10 µF = 220 ms. The first LED-on time is about 1.6 times as long as the others.

The 1.10 from the charging curve optional

Call the supply . During a charge from 0 V, the gap falls as

The charge ends when the gap is one third of the supply:

Divide both sides by :

Take the natural logarithm of both sides. The logarithm of one third is minus the logarithm of 3:

Multiply both sides by :

With and , , so .

What just happened?

The reset on this board has two jobs, and each job has its own transistor. Q22 holds Q at 0, so the output is low. Q23 holds DIS near 0 V, so C empties. Q21 inverts RESET for both of them. The table compares the board with the function table of the NE555 datasheet.

While RESET is lowNE555 datasheetQ21 and Q22Q21 to Q23
OutputLowOUT high, LED darkOUT high, LED dark
DischargeOnQ20 on only above 1/3Q23 on
CapacitorDischargesStays near 1/3Falls to near 0 V
First charge after the releaseA new timing cycleThe normal lengthAbout 220 ms

The output on this board is the opposite way up from pin 3, as Experiment 12 explained, so the LED is the output to compare. The first attempt held the output, and the discharge still followed the latch. S changes the latch, and the trigger comparator sets S whenever CAP is below 1/3, during a reset too. A reset that acts only on the latch shares the latch with S. Q23 acts on DIS directly, after the latch, so no signal from the comparators reaches it. That is how RESET overrides the other inputs, as the datasheet says.

Going further

A square wave on RESET turns the timer on and off. Set channel 1 of the function generator to a square wave at 1 Hz, low level 0 V and high level 5 V, with the load set to HiZ (Experiment 3 explains why). Take the RESET lead's end out of the rail, clip the generator's red lead on it, and clip the black lead to the inner bottom rail. Then switch on the output. The LED blinks for half a second and stays dark for half a second, and each burst starts with the long first charge. When you finish, switch off the output and put the lead's end back in the +5 V rail.

Quick check

Three questions on this experiment. They ask why the timer runs with RESET high, why two transistors were not enough, and why the first charge after a reset is longer.

1. The RESET lead is in the +5 V rail, and the timer runs because…

Current through Q21's 10 kΩ turns it on, and it holds RST near 0 V. Q22 and Q23 then get no base current, so the latch and Q20 work as in Experiment 12.

2. With only Q21 and Q22, CAP stops near 1/3 during a reset, because…

Q22 holds only Q. Gate 2 still takes S, and the trigger comparator sets S whenever CAP is below 1/3. So Q20 turns off at 1/3 and C charges again. Q23 holds DIS without the latch.

3. After a full reset, the first LED-on time is about 220 ms instead of 139 ms, because…

A normal charge halves the gap between the supply and CAP, which takes 0.69 RC. From 0 V the gap falls to one third, which takes 1.10 RC.

Before moving on

This is the last experiment of Stage Three, and the breadboard prototype is complete. The board now has all eight pins of the NE555: the two rails for pins 8 and 1, the five leads for pins 2, 3, 4, 6 and 7, and the divider's 2/3 tap for pin 5, CONTROL. Twenty-three transistors do the work of the chip, and each block was tested on the bench before the next one went in. Stage Four puts the same circuit on a printed circuit board. Experiment 14: The Master Schematic draws the whole circuit as one schematic, with a designator for each part.

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