Source: https://fullstackelectronics.com/experiments/16-the-smoke-test

# Experiment 16: The Smoke Test

The third step from the breadboard to a printed circuit board. Run the KiCad schematic in KiCad's simulator with the outside parts of Experiment 12. Compare its timing with your breadboard, and test the reset of the board.

Experiment 15 ended with the master schematic in KiCad and zero errors from the electrical rules checker, ERC. ERC checks that each connection obeys the rules of connection. It does not check that the circuit runs as a timer. For this board that is important, because the board is not a copy of the breadboard. Experiment 14 made five changes, and no breadboard has run them. An error in them shows only when the boards come back from the factory, some weeks after the order. A simulator can test the changes before the order. It calculates the voltage on each net of the schematic, step by step in time, and plots the result as an oscilloscope does. This experiment connects the outside parts of Experiment 12 to a copy of the KiCad project and runs it in KiCad's simulator. Then it compares the timing with your breadboard and tests the reset of the board. The name of the experiment comes from the first power-up of a new circuit, the smoke test. Here the first power-up is in the simulator.

### Resources

- [KiCad simulation project](https://fullstackelectronics.com/experiments/files/16-kicad-sim.zip)ZIP · KiCad 10 project `555-sim`The project of Experiment 15 with the changes of this experiment: J1 and the test pads excluded from simulation, and the test bench with V2 on the root sheet. Open it to compare with your copy, or to run the simulation without the steps.
- [KiCad schematic](https://fullstackelectronics.com/experiments/files/15-kicad-schematic.zip)ZIP · the project of Experiment 15The start point, if you do not have your project from Experiment 15.

### You will need

- [ ] 1×A computer with KiCad 10. The simulator, ngspice, is part of KiCad.
- [ ] 1×Your KiCad project from Experiment 15, or the second ZIP in the box “Resources”
- [ ] *No power supply or oscilloscope. This experiment is on the computer.*

## What a simulator does

The lead said that a simulator calculates the voltage on each net. It starts from the [netlist](https://fullstackelectronics.com/reference/glossary.html.md#netlist) that KiCad makes from the schematic. Each part gives a rule for the currents in its pins. For a resistor the rule is Ohm's law. For a capacitor, the current changes the voltage across it. For a transistor, the rule is its model: a set of equations with measured constants. The simulator finds the voltages that obey all the rules at one instant. Then it moves the time forward by a small step and calculates again. KiCad calls this a transient analysis, TRAN.

KiCad's simulator is ngspice, a free program that comes from SPICE. The box “Where SPICE comes from” gives its history. ngspice needs a model for each symbol and a source for each supply. The table gives what the schematic of Experiment 15 has and what it needs.

| Parts | What the simulator uses | What to do |
|----|----|----|
| R1 to R21, C1 | The value. KiCad finds the model of a resistor or a capacitor from its designator and value. | Nothing |
| Q1 to Q23 | KiCad's built-in NPN or PNP model, from two fields of the MMBT3904 and MMBT3906 symbols | Nothing |
| J1, TP1 to TP5 | Nothing. KiCad has no model for a connector or a test pad. | Exclude them from simulation |
| The 5 V supply, RA, RB and C | Nothing. They are not on the schematic, because on the breadboard they are outside the 555. | Add them as a test bench |

Figure 16-1 shows how the simulator gets a transistor. The MMBT3904 symbol of the KiCad library has two simulation fields. `Sim.Device` selects KiCad's built-in NPN model. `Sim.Pins` connects each pin of the symbol to a pin of the model. Pin 1 goes to the base B, pin 2 to the emitter E and pin 3 to the collector C. These are the same pin numbers that go to the pads of the SOT-23 footprint. A wrong pin map connects the right nets to the wrong legs, as a wrong footprint does.

![Top left, Q19 on the root sheet: an NPN symbol with pin 1 on the base, marked B, with a wire from R14; pin 3 on the collector, marked C, with a wire up to OUTPUT; and pin 2 on the emitter, marked E, with a wire down to GND. An arrow goes right to the simulation fields of the symbol: a table with Sim.Device NPN and Sim.Pins 1=B 2=E 3=C, and the note symbol pin 1 is model pin B, and so on. An arrow goes down to what the simulator connects: a table titled model pin, in SPICE order, with C to OUTPUT, pin 3; B from R14, pin 1; and E to GND, pin 2, and the note model: KiCad's built-in NPN.](https://fullstackelectronics.com/experiments/img/16-sim-pins.svg)

**Figure 16-1:** How the simulator connects Q19. The field `Sim.Pins` gives the model pin for each pin of the symbol, and the model takes its pins in the order C, B, E.

In the Schematic Editor, double-click a transistor and click Simulation Model… to see the two fields. The tab Pin Assignments shows the pin map. In the simulator, Simulation → Show SPICE Netlist… shows the text that KiCad gives to ngspice, with one line for each part.

#### The transistor model

KiCad's built-in NPN and PNP models use the default constants of ngspice. They describe a general small transistor with a current gain of 100. They are not a model of the MMBT3904. For this experiment that is sufficient, because RA, RB, C and the divider set the timing. I also ran the simulation with published models of the 2N3904 and 2N3906, the TO-92 versions of the same transistors. The period changed from 209.30 ms to 209.29 ms, and the turning points by less than 5 mV. For currents, speeds and limits, use the model of the part. As the KiCad manual says, semiconductor manufacturers often supply SPICE models of their parts.

## Make a copy for the simulation

The table gave two tasks: exclude J1 and the test pads, and add a test bench. Both change the schematic, so they go in a copy of the project. The test bench joins THRESHOLD and TRIGGER, as the wire from pin 6 to pin 2 did on the breadboard. In the master project, the PCB Editor of Experiment 18 would get that wire as a connection on the board. So the master project stays as it is.

1.  **Copy the project.** Close KiCad. Copy the folder of your project and give the copy the name `555-sim`. In KiCad, open `555-sim/555.kicad_pro`, then the Schematic Editor.
2.  **Exclude J1.** Open the sheet UI. Double-click J1 to open Symbol Properties, select the checkbox Exclude from simulation, and click OK. KiCad draws J1 grey with a small simulation icon.
3.  **Exclude the test pads.** On the root sheet, do the same for TP1 to TP5.

## Build the test bench

The copy is now ready for the parts that the breadboard had outside the 555. Figure 16-2 shows them around the schematic. They are the parts of Experiment 12 with KiCad designators. V1 is the 5 V supply, RA and RB are 10 kΩ, and CT is the 10 µF capacitor C. V2 is for the reset test, later in this experiment. CONTROL stays open, as on the breadboard.

[![Schematic. In the middle, a pale rounded box: the KiCad schematic of Experiment 15, six sheets, 23 transistors, with the note J1 and TP1 to TP5 excluded from simulation. Numbered pin badges sit on its edges: 8 at the top, 1 at the bottom, 5 CONTROL, open, and 4 on the left, and 3, 7, 6 and 2 on the right. At the far left, V1, a circle with plus and minus, 5 volts, connects a red +5 V line along the top to a blue ground line along the bottom, which has one ground symbol. Pin 8 goes up to the +5 V line and pin 1 down to the ground line. V2, a second source labelled reset test, connects the ground line to a wire labelled RESET into pin 4. On the right, RA, 10 kilohms, goes down from the +5 V line to the wire from pin 7, DISCHARGE. RB, 10 kilohms, goes from there down to a node labelled CAP. The wires from pin 6, THRESHOLD, and pin 2, TRIGGER, join and go to CAP. CT, 10 microfarads, goes from CAP down to the ground line. The wire from pin 3, OUTPUT, hops over the RA wire and ends at the right edge in a green circle marked plot. A second green circle marked plot is on CAP. A line at the top reads: test bench, for simulation only: V1, V2, RA, RB and CT.](https://fullstackelectronics.com/experiments/img/16-bench.svg)](https://fullstackelectronics.com/experiments/img/16-bench.svg)

**Figure 16-2:** The test bench around the KiCad schematic. The pale outline is the schematic of Experiment 15, with the pin numbers of J1. Everything outside it is the test bench. The simulator plots the two nets marked plot.

Put the test bench in the empty space at the left of the root sheet, next to the sheet symbols.

1.  **Place the supply.** Press A, type `VDC`, and place the symbol VDC from the library `Simulation_SPICE`. Press U and type `V1`. Press V and type `5`, the voltage of the source. Press P and connect a `+5V` symbol to its + pin and a `GND` symbol to its − pin.
2.  **Place RA, RB and CT.** Place two `R` and one `C` from the library `Device`. Give them the designators `RA`, `RB` and `CT`, and the values `10K`, `10K` and `10u`. Wire them in a column from a `+5V` symbol to a `GND` symbol: RA at the top, then RB, then CT.
3.  **Name the nets.** Press L and put the label `DISCHARGE` on a wire from the point between RA and RB. Put the labels `THRESHOLD` and `TRIGGER` on wires from the point between RB and CT. Each label joins its wire to the net with the same name on the root sheet. So the three labels connect the test bench to pins 7, 6 and 2.
4.  **Run ERC.** ERC gives one warning: “Both THRESHOLD and TRIGGER are attached to the same items; THRESHOLD will be used in the netlist”. In this copy the warning is correct, because the test bench joins the two nets on purpose. In the master project, the same warning shows a fault.

[![The test bench as KiCad plots it. A blue note at the top reads Test bench: for simulation only. On the left, V1, a round yellow source marked 5, between a +5V symbol above and a GND symbol below. On the right, a column from a +5V symbol: RA, 10K, then a junction with a wire to the label DISCHARGE, then RB, 10K, then a junction with wires to the labels TRIGGER on the left and THRESHOLD on the right, then CT, 10u, down to a GND symbol. At the bottom left, V2, a round source with a pulse drawn in it, marked VPULSE, with its top wire going to the label RESET and its bottom to a GND symbol.](https://fullstackelectronics.com/experiments/img/16-bench-kicad.svg)](https://fullstackelectronics.com/experiments/img/16-bench-kicad.svg)

**Figure 16-3:** The test bench as KiCad plots it, at the left of the root sheet of `555-sim`. V2 at the bottom comes in the reset test.

## Run the simulation

With the test bench, the schematic is a complete circuit: the breadboard of Experiment 12 with the five changes of Experiment 14. The simulator runs in a window of its own.

1.  **Open the simulator.** In the Schematic Editor, select Inspect → Simulator.
2.  **Make a transient analysis.** Select Simulation → New Analysis Tab… and choose TRAN, the transient analysis. Type `20u` for the time step and `1` for the final time, in seconds. Select Use initial conditions, so that each voltage starts at 0 V, as at power-up with an empty C. Click OK.
3.  **Run the analysis.** Select Simulation → Run Simulation, or press R. KiCad gives the netlist to ngspice and shows the messages of ngspice in the window under the plot. The run can take some seconds.
4.  **Plot CAP and OUTPUT.** Select Simulation → Probe Schematic…, or press P. In the Schematic Editor, click the wire between RB and CT, then the OUTPUT wire. The plot shows `V(/THRESHOLD)`, which is CAP, and `V(/OUTPUT)`.
5.  **Read the period and the turning points.** In the list of signals, select Cursor 1 and Cursor 2 for `V(/OUTPUT)`. Drag the two cursor markers to two rising edges, one period apart. The cursor table gives the time between them. Use the cursors on `V(/THRESHOLD)` to read the turning points.

[![Graph of two signals against time, from 0 to 1000 milliseconds, each with its own scale from 0 to 5 volts. Top, OUTPUT: high at 5 volts from 0 to about 216 milliseconds, marked first charge 215.6 ms, with the note high while C charges. Then it alternates: low for about 70 milliseconds, high for about 139 milliseconds. One cycle near 700 to 910 milliseconds is marked one period 209.3 ms. Bottom, CAP: it rises in a curve from 0 volts to a dashed line at 3.333 volts, falls to a dashed line at 1.667 volts, and then goes up and down between the two dashed lines. It rises while OUTPUT is high and falls while OUTPUT is low.](https://fullstackelectronics.com/experiments/img/16-sim-astable.svg)](https://fullstackelectronics.com/experiments/img/16-sim-astable.svg)

**Figure 16-4:** The result of the simulation, the first second after power-up. OUTPUT is high while C charges, as on pin 3 of the NE555. CAP turns at 1.667 V and 3.333 V. The first charge starts from 0 V and takes 215.6 ms. After it, each period is 209.3 ms.

#### Time step and initial conditions

At a time step of 20 µs, one second of the circuit is 50 000 steps. A larger step makes the run faster and the edges less exact. At 100 µs the periods of this run go from 209.3 ms to 210.7 ms. Use initial conditions starts each voltage at 0 V. Without it, ngspice first calculates a steady state for the circuit and starts from there. Then the first charge does not start from an empty C, and the start of the plot does not match a power-up.

## Compare with the bench

Figure 16-4 has the three numbers that Experiment 12 measured on the breadboard: the period and the two turning points. The table compares them with the calculation and with the NE555.

| Measurement | Calculated, Experiment 12 | Simulation | Breadboard, Experiment 12 | NE555, Experiment 1 |
|----|----|----|----|----|
| Period | About 208 ms | 209.3 ms | 192.59 ms | 200.46 ms |
| CAP minimum | About 1.67 V | 1.667 V | 1.56 V | 1.68 V |
| CAP maximum | About 3.33 V | 3.333 V | 3.12 V | 3.34 V |
| OUTPUT while C charges | High, Experiment 14 | High, 5.00 V | Low, the LED is on | High |

The simulation agrees with the calculation to 0.7 %. The charge takes 138.8 ms, and the calculation gives 138.6 ms. The discharge takes 70.5 ms, 1.2 ms more than the 69.3 ms of the calculation. During the discharge, Q20 holds DIS at 0.04 V. So C discharges towards 0.04 V, and it takes a little longer to reach 1/3 of the supply.

The turning points are at 1/3 and 2/3 of 5 V to 1 mV. In the simulation, the two transistors of each pair are identical, and each resistor has its exact value. Experiment 12 gave two possible causes for the lower turning points of the breadboard: the offsets of the comparators and the tolerances of the divider. The simulation has neither of them. The breadboard period is 8 % shorter than the simulation. Experiment 12 gave the causes of a difference of this size: the tolerances of RA, RB and C, the turning points and the measurement.

The run also tests four of the five changes of Experiment 14:

- Q19 takes Q̄, so OUTPUT is high while C charges, as on pin 3. On the breadboard, Q19 takes Q, and OUTPUT is low while C charges.
- R21 pulls OUTPUT up to 5.00 V. Nothing loads OUTPUT in this run.
- The 4.7 kΩ divider puts the turning points at 1/3 and 2/3.
- Nothing drives RESET in this run. R16 holds it high, and the timer runs.

## Test the reset of the board

The fifth change of Experiment 14 is Q23 on S, for the reset. To test it, V2 holds RESET low for a time, as the RESET lead did in Experiment 13. A pulse source does this: it gives one voltage, then a second voltage for a set time, then the first voltage again.

1.  **Place V2.** In the Schematic Editor, place the symbol VPULSE from the library `Simulation_SPICE` under V1, with the designator `V2`. Connect its + pin to a wire with the label `RESET`, and its − pin to a `GND` symbol.
2.  **Set the pulse.** Double-click V2, click Simulation Model…, and type these values in the tab Parameters: `y1` = `5`, `y2` = `0`, `td` = `350m`, `tr` = `1u`, `tf` = `1u`, `tw` = `250m`, `per` = `2`. They are the start voltage, the pulse voltage, the delay, the times of the two changes, the width of the pulse and its period. V2 then gives 5 V, then 0 V from 350 ms to 600 ms, then 5 V again.
3.  **Run the analysis again.** In the simulator, press R. Probe the RESET wire too.

[![Graph of three signals against time, from 0 to 1000 milliseconds, each with its own scale from 0 to 5 volts. A pale band from 350 to 600 milliseconds is marked RESET held low. Top, RESET: 5 volts, 0 volts in the band, 5 volts after it. Middle, OUTPUT: it alternates as before until 350 milliseconds, falls at the start of the band and stays at 0.04 volts through the band. At 600 milliseconds it rises and stays high for a span marked first charge 203.8 ms, then it alternates again. Bottom, CAP: it charges and discharges as before, falls in a curve through the band to 0.32 volts at 600 milliseconds, then rises from there to the upper turning point.](https://fullstackelectronics.com/experiments/img/16-sim-reset.svg)](https://fullstackelectronics.com/experiments/img/16-sim-reset.svg)

**Figure 16-5:** The reset test of the board. RESET is low from 350 ms to 600 ms. OUTPUT goes low at once and stays at 0.04 V. Q20 empties C to 0.32 V. After the release, the first charge takes 203.8 ms.

Figure 16-5 shows what the NE555 does during a reset: OUTPUT is low and C empties. The reset block holds Q at 0 through Q22 and S at 0 through Q23, so Q̄ stays at 1. When RESET goes high, C charges from 0.32 V in place of 1.67 V. So the first charge takes 203.8 ms in place of 138.8 ms. This is the long first charge of Experiment 13.

## A reset without Q23

Figure 16-5 shows that the reset works with Q23. Experiment 14 gave the reason for Q23 on S: without it, OUTPUT goes high during a reset. The simulator can test that reason with one checkbox.

1.  **Exclude Q23.** Open the sheet Reset, double-click Q23 and select Exclude from simulation.
2.  **Run the analysis again.** In the simulator, press R.

[![The graph of Figure 16-5 for the run without Q23. RESET is the same. OUTPUT falls at 350 milliseconds, but 45 milliseconds later, marked 45 ms, it rises again and settles at 3.39 volts until the end of the band. CAP falls from 350 milliseconds until it reaches 1.67 volts and stays flat at 1.67 volts until 600 milliseconds. After the band, OUTPUT and CAP alternate as before, with no long first charge.](https://fullstackelectronics.com/experiments/img/16-sim-reset-no-q23.svg)](https://fullstackelectronics.com/experiments/img/16-sim-reset-no-q23.svg)

**Figure 16-6:** The reset test with Q23 excluded from simulation. 45 ms after RESET goes low, OUTPUT rises and settles at 3.39 V. CAP stays at 1.67 V, 1/3 of the supply, until the release.

Figure 16-7 shows the reset circuit of the board at gate level, with Q23 pale. Follow the green numbers.

[![Gate-level schematic. On the left, two NOR gates form the latch: Gate 1 takes R and makes Q, Gate 2 takes S and makes Q-bar, with the feedback wires crossing between them. S comes in from the left, with the note from the trigger comparator, and green marker 2. The transistor Q23 on S is drawn pale, labelled Q23, excluded. Q is held by Q22, whose base goes to the name RST, with green marker 1. Q-bar, with green marker 3, goes right to R14 and R15. R14 drives Q19, whose collector is OUTPUT with the pull-up R21 from +5 V, and green marker 5 is beside Q19. R15 drives Q20, whose collector is DISCHARGE, with the note to RB and C, and green marker 4. One ground line runs along the bottom with one ground symbol.](https://fullstackelectronics.com/experiments/img/16-reset-no-q23.svg)](https://fullstackelectronics.com/experiments/img/16-reset-no-q23.svg)

**Figure 16-7:** The latch, Q19 and Q20 of the board, with Q23 excluded from simulation. During the reset, RST is high and Q22 is on. The numbers match the steps.

1.  RESET goes low, and Q22 holds Q at 0. Gate 2 has 0 on both inputs, so Q̄ is 1. Q19 holds OUTPUT low, and Q20 empties C.
2.  CAP falls to 1.67 V, 1/3 of the supply. The trigger comparator makes S 1.
3.  S is an input of Gate 2, so Q̄ falls.
4.  Q20 starts to turn off, and C stops its discharge. RA and RB charge C again, and CAP rises above 1.67 V. Then the trigger comparator lowers S, and Q̄ rises again.
5.  Q19 also starts to turn off, and OUTPUT rises. Steps 2 to 4 work against each other until they balance: CAP at 1.67 V, Q̄ at 0.78 V and OUTPUT at 3.39 V.

With Q23, S stays at 0 during the reset, so step 2 cannot change the latch. That is the reason for Q23 on S. Clear the checkbox Exclude from simulation on Q23 before you continue.

#### Where SPICE comes from, and where to learn more

SPICE means Simulation Program with Integrated Circuit Emphasis. Laurence Nagel wrote it at the University of California, Berkeley, in the group of Donald Pederson, in the early 1970s. It was for the design of integrated circuits. ngspice is a free program that comes from Berkeley SPICE, and KiCad includes it.

- [The section Simulator of the Schematic Editor manual](https://docs.kicad.org/10.0/en/eeschema/eeschema.html#simulator) gives each analysis, the model fields and the plot tools.
- [The ngspice manual](https://ngspice.sourceforge.io/docs.html) gives each model and its constants.

## Quick check

Three questions on this experiment. They ask why the test bench is in a copy, why the discharge is longer than calculated, and what Q23 does.

1\. Why does the test bench go in a copy of the project?

KiCad can simulate only a project with one sheet

The test bench joins THRESHOLD and TRIGGER, and in the master project that connection would go to the board

The simulator changes the values of the parts in the project

A wire on the schematic is a connection for the PCB Editor. The test bench needs THRESHOLD and TRIGGER joined, as on the breadboard. On the board they must stay two nets, so the test bench lives in `555-sim`.

2\. In the simulation the discharge takes 70.5 ms, and the calculation gives 69.3 ms. Why?

The simulator calculates with a time step that is too large

The 4.7 kΩ divider moves the lower turning point

Q20 holds DIS at 0.04 V, so C discharges towards 0.04 V

The calculation takes DIS at 0 V. Q20 in saturation holds it at 0.04 V. C discharges through RB towards that voltage, so it takes a little longer to fall from 2/3 to 1/3 of the supply.

3\. Without Q23, RESET goes low. What does OUTPUT do?

It stays low until RESET goes high

It goes low, then rises when CAP reaches 1/3 of the supply, and settles near 3.4 V

It continues to run at 209.3 ms

When CAP falls to 1/3, the trigger comparator makes S 1, and S lowers Q̄. Q19 starts to turn off, so OUTPUT rises. Q23 holds S at 0 during a reset, so this cannot occur on the board.

## Before moving on

The KiCad schematic runs as a timer in the simulator. Its period is 209.3 ms, 0.7 % from the calculation. CAP turns at 1/3 and 2/3 of the supply, OUTPUT is high while C charges, as on pin 3, and a reset holds OUTPUT low. Each of the five changes of Experiment 14 is in a run. That is the third step from the breadboard to the board. Keep `555-sim`: if you change the master schematic, make the same change in the copy and run the simulation again. The parts still have no size or shape on the board. [Experiment 17: Going Surface-Mount](https://fullstackelectronics.com/experiments/17-going-surface-mount.html.md) gives each part a footprint.