Source: https://fullstackelectronics.com/experiments/15-schematic-capture

# Experiment 15: Schematic Capture

The second step from the breadboard to a printed circuit board. Enter the master schematic in KiCad, sheet by sheet, and check it with the electrical rules checker until it reports no errors.

Experiment 14 drew the master schematic on paper: five sheets, the named nets and a list of the parts. A factory cannot make a board from paper. It needs files that give the exact position of each copper pad, track and hole. KiCad is a free program that goes from a schematic to those files. You draw the circuit in KiCad, and KiCad checks its connections. Then you place the parts on a board outline and draw the copper between them, and KiCad writes the files for the factory. The link between the two halves is the [netlist](https://fullstackelectronics.com/reference/glossary.html.md#netlist): a list of each net and the pins on it, which KiCad makes from the schematic. The board editor reads the netlist and shows which pads to connect, so each track on the board comes from a wire in the schematic. So the schematic comes first. This experiment enters the master schematic in KiCad and checks it with the electrical rules checker, ERC. The result is a KiCad schematic that has zero ERC errors and the same nets as the net table of Experiment 14.

### Resources

- [Master schematic](https://fullstackelectronics.com/experiments/files/14-master-schematic.pdf)PDF · 7 pages, A4 landscapeThe print from Experiment 14. It is the map for each sheet that you enter.
- [KiCad schematic](https://fullstackelectronics.com/experiments/files/15-kicad-schematic.zip)ZIP · KiCad 10 project, six sheetsThe schematic that the boards were made from, in July 2026. Open it to compare with your capture, or to start Experiment 16 without a capture.
- [KiCad schematic, plotted](https://fullstackelectronics.com/experiments/files/15-kicad-schematic.pdf)PDF · 6 pages, A4The same six sheets as KiCad prints them, one to a page.

### You will need

- [ ] 1×A computer with KiCad 10, free from [kicad.org/download](https://www.kicad.org/download/) for Windows, macOS and Linux
- [ ] 1×The print of the master schematic, the first PDF in the box “Resources”
- [ ] *No power supply or oscilloscope. This experiment is on the computer.*

## KiCad

KiCad is free and open source, and it runs on Windows, macOS and Linux. This course uses version 10. Each step of Stage Four from here to the order uses a part of KiCad. The table gives them.

| Step | Part of KiCad | Experiment |
|----|----|----|
| Enter the schematic and check its connections | Schematic Editor and its electrical rules checker (ERC) | 15 |
| Simulate the circuit before any part exists | Simulator, in the Schematic Editor | 16 |
| Give each part a footprint | Footprint assignment, in the Schematic Editor | 17 |
| Place the parts and draw the copper | PCB Editor | 18 |
| Check the board and write the files for the factory | Design rules checker (DRC) and [Gerber](https://fullstackelectronics.com/reference/glossary.html.md#gerber) plot, in the PCB Editor | 19 |

A KiCad project is a folder of text files with one name: the project file `555.kicad_pro`, one `.kicad_sch` file for each sheet of the schematic, and the board file `555.kicad_pcb`. Because the files are text, git can keep the history of a design, as it does for code. The first window is the Project Manager, which opens each editor. This experiment uses the Schematic Editor only.

#### Where to learn more about KiCad

- [Getting Started in KiCad](https://docs.kicad.org/10.0/en/getting_started_in_kicad/getting_started_in_kicad.html), the official tutorial. It takes one small circuit from the schematic to the files for the factory. Its part 2 is the schematic.
- [The Schematic Editor manual](https://docs.kicad.org/10.0/en/eeschema/eeschema.html). Its sections [Hierarchical schematics](https://docs.kicad.org/10.0/en/eeschema/eeschema.html#hierarchical-schematics) and [Electrical rules checking](https://docs.kicad.org/10.0/en/eeschema/eeschema.html#erc) give more detail on the two topics of this experiment.
- [The KiCad forum](https://forum.kicad.info/), for questions.
- In KiCad, Help → List Hotkeys shows each key. This page uses the default keys.

## Symbols and footprints

The Schematic Editor draws each part as a symbol. A symbol has pins, and each pin has a number, a name and an electrical type. The board uses a [footprint](https://fullstackelectronics.com/reference/glossary.html.md#footprint) for each part: the copper pads that the part is soldered on. Each pad has a number too. KiCad connects pin 1 of the symbol to pad 1 of the footprint, pin 2 to pad 2, and so on. The names B, C and E have no effect on that connection. Figure 15-1 shows why this matters.

![Two rows. Top row: the KiCad symbol MMBT3904, an NPN transistor with pin 1 on the base B, pin 2 on the emitter E and pin 3 on the collector C. An arrow labelled pin n to pad n goes to the SOT-23 footprint, three copper pads: pad 1 at the top left, pad 2 at the bottom left, pad 3 at the right. Beside the pads are the nets: B on pad 1, E on pad 2, C on pad 3. On the right, the MMBT3904 part from above, a black body with legs B at the top left, E at the bottom left, C at the right. Note: each net is on the leg of its name. Bottom row: the KiCad symbol 2N3904, with pin 1 on the emitter, pin 2 on the base and pin 3 on the collector. With the same SOT-23 footprint, the nets are E on pad 1, B on pad 2 and C on pad 3, but the part still has B on pad 1 and E on pad 2. Note: the base and emitter nets change places.](https://fullstackelectronics.com/experiments/img/15-pin-numbers.svg)

**Figure 15-1:** A symbol connects to a footprint by pin numbers. Top: the MMBT3904 symbol numbers its pins as the SOT-23 package. Bottom: the 2N3904 symbol numbers its pins as the TO-92 package of the breadboard.

The board uses the MMBT3904 and MMBT3906, the 2N3904 and 2N3906 in the SOT-23 package. Use the symbols with those names, in the library `Transistor_BJT`. They number the pins 1 B, 2 E, 3 C, as the SOT-23 package, and they already name the SOT-23 footprint. The symbols 2N3904 and 2N3906 number the pins 1 E, 2 B, 3 C, for the TO-92 package. The symbols Q_NPN and Q_PNP in the library `Device` use the letters B, C and E as pin numbers. No footprint has pads with those names.

ERC does not compare a symbol with a footprint. With the 2N3904 symbol, the schematic passes ERC, and each transistor on the board has its base and emitter changed. So choose the symbol by its name before you place the first transistor.

## Practice: the switch of Experiment 3

The MMBT symbols are the first rule for the capture. Before the 555 with its twenty-three transistors, practise the Schematic Editor and ERC on a circuit that you know. Figure 15-2 is the transistor switch of Experiment 3 with KiCad's designators. J1 is a three-pin header for +5 V, IN and ground. J2 is a one-pin header for OUT. On the 555 board, J1 is the eight pins.

![Schematic of the practice circuit. J1, a three-pin header on the left: pin 1 goes up to a red line labelled +5V along the top, pin 2 is IN, pin 3 goes down to a blue line labelled GND along the bottom, which has one ground symbol. IN goes through R1, 10 kilohms, to the base of Q1, an MMBT3904. Q1's emitter goes to the GND line. R2, 1 kilohm, connects the +5V line to Q1's collector. The collector is OUT, which goes right to J2, a one-pin header. A PWR_FLAG, a small diamond on a stem, sits on the +5V line and another on the GND line.](https://fullstackelectronics.com/experiments/img/15-practice.svg)

**Figure 15-2:** The practice circuit: the transistor switch of Experiment 3 with two pin headers. The two PWR_FLAG symbols come in step 6.

1.  **Make a project.** In the Project Manager, select File → New Project, choose the Default template, and give the project the name `switch`. Double-click `switch.kicad_sch` to open the Schematic Editor.
2.  **Place the parts.** Press A to open the Choose Symbol dialog. Type `MMBT3904`, select it and click on the sheet to place it. In the same way, place two `R` from the library `Device`, one `Conn_01x03_Pin` and one `Conn_01x01_Pin` from the library `Connector`. Press R to turn a part while you place it, and X to turn J2 round so that its pin points left.
3.  **Give each part its designator and value.** KiCad gives each new part the next free designator. Put the pointer on a part and press U to change its designator to the one in Figure 15-2. Press V to change a value: `10k` for R1 and `1k` for R2.
4.  **Draw the wires.** Press W, click on the end of a pin, and click on the end of the next pin. A wire connects only at its ends. Draw each wire of Figure 15-2.
5.  **Add the supply.** Press P and place a `+5V` symbol on the wire from J1 pin 1 and a `GND` symbol on the wire from J1 pin 3. A power symbol gives its net a name. Each `+5V` symbol on any sheet is on the same net.
6.  **Run ERC.** Select Inspect → Electrical Rules Checker, then click Run ERC. ERC gives two errors, “Input Power pin not driven by any Output Power pins”, one on the `+5V` symbol and one on the `GND` symbol. Press P again and place a `PWR_FLAG` on the +5V wire and one on the GND wire. Run ERC again. It reports no errors and no warnings.
7.  **Make an error on purpose.** Delete the wire from R1 to Q1's base and run ERC. It gives three errors: “Pin not connected” on R1 pin 2 and on Q1 pin 1, and “Input pin not driven by any Output pins” on Q1 pin 1. ERC puts a marker on the sheet at each error. Then undo the delete and run ERC again.

#### Why ERC needs a PWR_FLAG

Each pin of a symbol has an electrical type, such as input, output, passive or power input. ERC checks the pins on each net against a table of the types that can connect. The pin of a `+5V` or `GND` symbol is a power input, so ERC looks for a power output on the same net. On this circuit the supply comes from the bench power supply through J1, and J1's pins are passive. A PWR_FLAG has one power output pin. It tells ERC that the net gets power from outside the schematic. ERC is similar to a linter: it checks rules of connection. It cannot tell if the circuit does what it must do.

## How the sheets connect

The practice circuit fits on one sheet. The KiCad project of the 555 has a root sheet and five sheets under it. Experiment 14 drew the master schematic in the same way, as a top sheet and block sheets. Figure 15-3 shows how one sheet connects to the root sheet.

![Two panels. Left, the root sheet 555.kicad_sch: a pale box labelled SR Latch, with File: sr_latch.kicad_sch under it. On its left edge are two sheet pins, R and S, drawn as small flags; on its right edge two more, QB and Q. A wire leaves each sheet pin, and each wire has a local label with the same name: R, S, QB, Q. Right, the SR Latch sheet sr_latch.kicad_sch: hierarchical labels R and S on the left and QB and Q on the right, drawn as the same flags, on wires into a dashed box labelled Q15 to Q18, R8 to R13. A +5V power symbol sits above the box and a GND symbol below it. A green arrow labelled double-click goes from the sheet symbol on the left to the sheet on the right.](https://fullstackelectronics.com/experiments/img/15-sheets.svg)

**Figure 15-3:** A sheet on the root sheet. The box is a sheet symbol: it stands for the file `sr_latch.kicad_sch`. Each sheet pin on the box connects to the hierarchical label with the same name inside that sheet.

KiCad has four ways to connect by name. The 555 project uses the first three.

| Object | Key | What it connects |
|----|----|----|
| Hierarchical label | H | A net inside a sheet to the sheet pin with the same name on the sheet symbol |
| Local label | L | All wires with the same name on one sheet. The root sheet uses them for the test pads and J1. |
| Power symbol | P | All `+5V` on all sheets, and all `GND`. So no sheet has a sheet pin for the supply. |
| Global label | Ctrl+L (⌘+L on a Mac) | All wires with the same name on all sheets. The project does not use them. |

The table gives each sheet of the project. The parts and their designators are the same as in Experiment 14. The sheet UI holds J1, the eight pins of the board, and the two PWR_FLAG symbols. On the top sheet of your print, J1 is the eight pin badges on the board outline.

[TABLE]

Two names differ from the print. The project writes Q̄ as QB. In the threshold comparator, the input from the 2/3 tap is the hierarchical label REF23. On the root sheet, a wire connects its sheet pin to the 2/3 tap, which has the local label CONTROL. A local label has priority over a hierarchical label, so the net name is CONTROL, as in the net table.

## Enter the 555

With the four kinds of connection, you can enter the whole schematic. Do one sheet at a time, and run ERC after each sheet. One sheet has few errors to find. Twenty-three transistors at once can have many.

1.  **Make the project.** Select File → New Project in the Project Manager, choose the Default template, and give the project the name `555`. Open `555.kicad_sch`, the root sheet.
2.  **Draw the sheet symbols.** Press S and click two corners of a box. In the Sheet Properties dialog, type the sheet name and the file name from the table after Figure 15-3. Make the five sheet symbols.
3.  **Enter a sheet.** Double-click the sheet symbol Threshold Comparator. Place its parts with A, `MMBT3904` for each NPN and `MMBT3906` for each PNP. Give each part the designator and value of page 2 of your print with U and V. For 4.7 kΩ, type `4.7k` or `4K7`. Draw the wires with W. Add `+5V` and `GND` with P. The positions on your sheet can be different from the print. The connections must be the same. Figure 15-5 shows this sheet in the KiCad project.
4.  **Add the hierarchical labels.** Press H and put a label on each input and output wire of the sheet, with the name from the table. Type each name with care: `THRESHOLD` and `THRESHOLD_` are two different nets.
5.  **Add the sheet pins.** Go back to the root sheet: right-click on an empty part of the sheet and select Leave Sheet. Right-click the sheet symbol and select Place Sheet Pin. KiCad puts the pin for the next hierarchical label on the pointer. Click on the edge of the box to place it. Continue until each label has its pin.
6.  **Run ERC.** The sheet pins are not connected yet, so ERC reports them, and the nets they will connect. With only the threshold comparator entered, ERC gives nine items:
    - “Pin not connected” on the three sheet pins
    - “Label connected to only one pin” on the labels THRESHOLD and REF23
    - “Input pin not driven by any Output pins” on the bases of Q1 and Q2, which are on those two nets
    - “Input Power pin not driven by any Output Power pins” for +5V and GND

    These go in steps 7 and 8. Correct each other error before you go on.
7.  **Enter the other sheets.** Do steps 3 to 6 for Trigger Comparator (page 3, Figure 15-6), SR Latch (page 4, Figure 15-7) and Reset (page 5, Figure 15-8). The UI sheet has J1, a `Conn_01x08_Pin`. Put a hierarchical label on pins 2 to 7, `+5V` on pin 8 and `GND` on pin 1. Put a PWR_FLAG on the wire of pin 8 and on the wire of pin 1. Figure 15-9 shows this sheet.
8.  **Complete the root sheet.** Place the parts of page 1 of your print: the divider R1 to R3, Q19 and Q20 with R14, R15 and R21, and C1. C1 is `C` from `Device`. Connect the sheet pins with wires. Where a wire is long, use a local label with L at each end. Place TP1 to TP5 (`TestPoint` from `Connector`) and put a local label on each with its net name.
9.  **Run ERC until it is clean.** The schematic is complete when ERC reports 0 errors and 0 warnings on all six sheets. The section “What ERC finds” gives the usual messages.
10. **Compare the nets.** Select View → Panels → Net Navigator. Put the pointer on a wire and press the backtick key, \`, to highlight its net. The Net Navigator lists each pin on that net. For each named net, compare the list with the net table on page 6 of your print.

Figure 15-4 is the root sheet of the KiCad project that the boards were made from. Your root sheet can have a different arrangement. Its connections must be the same.

[![The root sheet as KiCad plots it, with green wires and red symbols. At the left, two sheet symbols: Threshold Comparator in green with sheet pins REF23, THRESHOLD and R, and Trigger Comparator in orange with sheet pins REF13, S and TRIGGER. In the middle, the divider R1, R2 and R3, each 4K7, from a +5V symbol to a GND symbol. REF23 and a wire to the label CONTROL join between R1 and R2; REF13 joins between R2 and R3. R runs to the sheet symbol SR Latch, in purple, and S runs to SR Latch and to the sheet symbol Reset, in blue. SR Latch has QB and Q on its right; Q goes to Reset. QB goes through R14, 10K, to Q19 and through R15, 10K, to Q20. Q19's collector goes to the label OUTPUT and through R21, 4K7, to +5V. Q20's collector goes to the label DISCHARGE. At the right edge, labels THRESHOLD, CONTROL, DISCHARGE, OUTPUT, RESET and TRIGGER. C1, 0.1u, between +5V and GND. At the bottom left, a dashed box Test Points with TP1 to TP5 on labels S, R, Q, QB and REF13. At the bottom right, the sheet symbol UI with sheet pins TRIGGER, DISCHARGE, OUTPUT, THRESHOLD, CONTROL and RESET, each on a label of the same name.](https://fullstackelectronics.com/experiments/img/15-root-sheet.svg)](https://fullstackelectronics.com/experiments/img/15-root-sheet.svg)

**Figure 15-4:** The root sheet of the KiCad project, as KiCad plots it. The labels at the right edge and at the UI sheet symbol connect J1 to the circuit by name. The PDF in the box “Resources” has all six sheets.

Figures 15-5 to 15-9 are the five sheets under the root, in the order of the table after Figure 15-3. Each sheet has its own `+5V` and `GND` symbols, and a hierarchical label on each wire that leaves the sheet. Compare each figure with its page of your print. The connections are the same. The arrangement on the sheet is different in some places: for example, REF23 comes in from the right on the threshold sheet.

[![The sheet Threshold Comparator as KiCad plots it. A +5V line along the top. Under it, the PNP load Q5 and Q6, with their bases joined and Q6's base wired to its collector. Below them the NPN pair: Q1, with the hierarchical label THRESHOLD coming in from the left to its base, and Q2, with the hierarchical label REF23 coming in from the right to its base. The emitters of Q1 and Q2 join at the collector of Q4. Q3 and Q4 form the tail mirror at the bottom, with R4, 4K7, from +5V to Q3's collector, which is wired to the two bases. Q7, a PNP at the right, takes its base from Q5's collector. Q7's collector goes to the hierarchical label R and through R5, 4K7, to GND.](https://fullstackelectronics.com/experiments/img/15-sheet-threshold.svg)](https://fullstackelectronics.com/experiments/img/15-sheet-threshold.svg)

**Figure 15-5:** The sheet Threshold Comparator, Q1 to Q7, R4 and R5. Hierarchical labels THRESHOLD and REF23 in, R out. Page 2 of your print.

[![The sheet Trigger Comparator as KiCad plots it. A +5V line along the top. At the top left, the PNP tail mirror Q10 and Q11: Q10's base is wired to its collector, which goes through R6, 4K7, to GND. Q11's collector feeds the joined emitters of the PNP pair Q8 and Q9. The hierarchical label REF13 comes in from the left to Q8's base, and TRIGGER comes in from the right to Q9's base. Under the pair, the NPN load Q12 and Q13, with Q13's base wired to its collector. Q8's collector, on Q12's collector, goes to the base of Q14. Q14's emitter goes to GND, and its collector goes to the hierarchical label S and through R7, 4K7, to +5V.](https://fullstackelectronics.com/experiments/img/15-sheet-trigger.svg)](https://fullstackelectronics.com/experiments/img/15-sheet-trigger.svg)

**Figure 15-6:** The sheet Trigger Comparator, Q8 to Q14, R6 and R7. Hierarchical labels REF13 and TRIGGER in, S out. Page 3 of your print.

[![The sheet SR Latch as KiCad plots it, wide and low. On the left, the hierarchical label R goes through R8, 10K, to the base of Q15. Q15 and Q16 have their collectors joined under R12, 1K, from +5V, and that line goes up to the hierarchical label Q at the top right, and through R10, 10K, to the base of Q17. Q16's base comes through R9, 10K, from the QB line. In the middle, Q17 and Q18 have their collectors joined under R13, 1K, from +5V, and that line is QB, which goes to the hierarchical label QB at the right. The hierarchical label S comes in from the right through R11, 10K, to the base of Q18. All four emitters go to GND.](https://fullstackelectronics.com/experiments/img/15-sheet-latch.svg)](https://fullstackelectronics.com/experiments/img/15-sheet-latch.svg)

**Figure 15-7:** The sheet SR Latch, Q15 to Q18 and R8 to R13. Hierarchical labels R and S in, Q and QB out. Page 4 of your print.

[![The sheet Reset as KiCad plots it. The hierarchical label RESET comes in from the left. R16, 100K, goes from +5V down to the RESET wire, which continues through R18, 10K, to the base of Q21. R17, 10K, goes from +5V to Q21's collector. From that collector, R19, 10K, goes to the base of Q22, and R20, 10K, goes to the base of Q23. Q22's collector goes to the hierarchical label Q, and Q23's collector goes to the hierarchical label S, both at the top right. The emitters go to GND.](https://fullstackelectronics.com/experiments/img/15-sheet-reset.svg)](https://fullstackelectronics.com/experiments/img/15-sheet-reset.svg)

**Figure 15-8:** The sheet Reset, Q21 to Q23 and R16 to R20. Hierarchical label RESET in, Q and S out. Q21's collector has no label, so KiCad names its net Net-(Q21-C). Page 5 of your print.

[![The sheet UI as KiCad plots it. J1, Conn_01x08_Pin, with its eight pins numbered 1 to 8 down the left. Pin 1 goes to a GND symbol, with a PWR_FLAG on its wire. Pins 2 to 7 go to the hierarchical labels TRIGGER, OUTPUT, RESET, CONTROL, THRESHOLD and DISCHARGE. Pin 8 goes to a +5V symbol, with a PWR_FLAG on its wire.](https://fullstackelectronics.com/experiments/img/15-sheet-ui.svg)](https://fullstackelectronics.com/experiments/img/15-sheet-ui.svg)

**Figure 15-9:** The sheet UI: J1, the eight pins of the board, in the pin order of the NE555. The two PWR_FLAG symbols tell ERC that +5V and GND get power through J1. On your print, these are the pin badges of the top sheet, page 1.

## What ERC finds

The steps end when ERC is clean. These are the messages that a capture of this schematic usually gives, from KiCad 10.

| Message | Usual cause | Correction |
|----|----|----|
| Input Power pin not driven by any Output Power pins | No PWR_FLAG on +5V or GND | A PWR_FLAG on each supply wire of the UI sheet |
| Pin not connected | A wire end stops near a pin and does not touch it, or a sheet pin has no wire | Draw the wire again, from pin end to pin end |
| Sheet pin QB has no matching hierarchical label inside the sheet, with Hierarchical label Q_B has no matching sheet pin in the parent sheet | The label inside the sheet has a different spelling from the sheet pin | Type the same name on the label and on the pin |
| Label connected to only one pin | A local label has a different spelling from its partner, so it makes a net of its own | Correct the spelling |
| Input pin not driven by any Output pins | A base is on a net with no other pin, as the bases of Q1 and Q2 before the root sheet connects THRESHOLD and CONTROL | Connect the net. Then the error goes. |

ERC checks the rules of connection only. The 2N3904 symbol of Figure 15-1, a wrong value such as 10K for R4, and a wire to the wrong pin all pass ERC. Two wires that cross also pass, and they are not connected. KiCad connects two wires that cross only where it shows a junction dot. The comparison of the nets in step 10 finds these errors, because it compares your schematic with the design.

## Quick check

Three questions on this experiment. They ask what ERC can find, how a sheet connects, and why the PWR_FLAG is there.

1\. You place the 2N3904 symbol for each NPN and give it the SOT-23 footprint. ERC…

reports an error on each transistor, because the pin numbers do not agree with the footprint

reports no error, and on the board each NPN has its base and emitter changed

reports no error, and the board is correct, because the pin names are B, C and E

KiCad connects pin n to pad n. The 2N3904 symbol has E on pin 1 and B on pin 2. The MMBT3904 has its base on pad 1 and its emitter on pad 2. ERC does not compare symbols with footprints, so it cannot find this.

2\. Inside `sr_latch.kicad_sch` a hierarchical label is `Q_B`. On the root sheet the sheet pin is `QB`. ERC…

reports that the sheet pin has no matching label and the label has no matching sheet pin

connects them, because they are on the same sheet symbol

reports nothing until you make the board

A sheet pin connects only to the hierarchical label with the same name. With two names, there are two nets, and ERC gives an error on each side.

3\. Why does the UI sheet have two PWR_FLAG symbols?

They connect +5V and GND from the root sheet to the UI sheet

They put a current limit on the supply

The supply comes in through J1, which has passive pins, so ERC needs a mark that the two nets get power

The pins of the +5V and GND symbols are power inputs. ERC looks for a power output on each of the two nets. The bench supply is outside the schematic, so a PWR_FLAG on each net tells ERC that the net gets power.

## Before moving on

The master schematic is now a KiCad schematic. It has six sheets, ERC reports zero errors, and its nets are the nets of Experiment 14. That is the second step from the breadboard to the board. ERC shows that the connections obey the rules. It does not show that the circuit runs as a timer. [Experiment 16: The Smoke Test](https://fullstackelectronics.com/experiments/16-the-smoke-test.html.md) simulates this schematic in SPICE, before you buy any part.