Source: https://fullstackelectronics.com/experiments/11-the-sr-latch

# Experiment 11: The SR Latch

Build the second NOR gate and connect the two gates in a loop. Then drive it from the function generator, and watch it set, hold and reset.

Experiment 10 built one NOR gate from Q15 and Q16. Its OUT follows its inputs at every moment, so it cannot store anything. The timer must store one fact. After the trigger comparator's OUT falls, the capacitor must keep charging until the threshold comparator's OUT rises at 2/3 of the supply. So the timer needs a circuit that records which of the two comparators was high last.

In Experiment 2 that circuit was a latch made from the two NOR gates of a CD4001B chip. This experiment builds the second gate from Q17 and Q18. Then it connects the OUT of each gate to an input of the other gate. The pair then keeps its state after the input that set it returns to 0. Figure 11-1 shows the parts that this experiment adds, in colour.

![Logic diagram of the latch from two NOR gates. Gate 1, labelled Q15 and Q16, Experiment 10, is drawn pale, with its upper input from a terminal labelled R, threshold OUT, and its output Q on the right. Gate 2, labelled Q17 and Q18, this experiment, is drawn dark below it, with its lower input from a terminal labelled S, trigger OUT, and its output Q-bar on the right. Two dark feedback wires cross between the gates: from a junction on Q to Gate 2's upper input, and from a junction on Q-bar to Gate 1's lower input. A small arc marks where the two wires cross without a connection.](https://fullstackelectronics.com/experiments/img/11-latch-plan.svg)

**Figure 11-1:** The latch, with the parts that this experiment adds in colour. Experiment 10 built the pale gate.

### You will need

- [ ] 2×2N3904 NPN transistor, for Q17 and Q18
- [ ] 1×1 kΩ resistor, for the pull-up
- [ ] 2×10 kΩ resistor, one for each input of the new gate
- [ ] The board from Experiment 10: both comparators, the divider and the NOR gate in columns 28 to 33
- [ ] Jumper wire
- [ ] Bench power supply: one output at 5.00 V with a 50 mA current limit (the 5 V supply in the steps)
- [ ] Oscilloscope with three channels and two probes
- [ ] Function generator with two channels
- [ ] One BNC cable, one BNC T-piece and two BNC leads ending in mini-hook clips

## Two gates in a loop

The latch needs a second gate, and Gate 2 is a copy of the gate from Experiment 10. Q18 and Q17 share a 1 kΩ pull-up and an output, and each one has a 10 kΩ into its base. Two connections make the loop. Each one takes the output of one gate, through a 10 kΩ, to an input of the other gate. Figure 11-2 shows the result. In it, Q16 and Q17 are drawn turned round, with the base on the right. Their inputs then come in from the outputs.

![Schematic of the latch with four NPN transistors, one +5 volt line along the top and one ground at the bottom. Gate 1 on top: Q15 and Q16 share a 1 kilohm pull-up from the +5 volt line, and their joined collectors run right to a terminal labelled Q. Input R comes in from the left through a 10 kilohm resistor into Q15's base. Gate 2 below is the same circuit with Q18 and Q17, its 1 kilohm fed by a +5 volt wire that runs down on the right, and its output terminal labelled Q-bar. Input S comes in from the left through a 10 kilohm resistor into Q18's base. Q16 and Q17 have their bases on the right. A wire rises from the Q-bar line into a 10 kilohm resistor and Q16's base. A wire falls from the Q line, hops the Q-bar line, and runs into a 10 kilohm resistor and Q17's base. Gate 1's emitter line drops between Q18 and Q17, hops the Q-bar line, and joins Gate 2's emitter line above the ground symbol.](https://fullstackelectronics.com/experiments/img/11-latch-schematic.svg)

**Figure 11-2:** The latch. Gate 1 makes Q, and Gate 2 makes Q̄. Q goes to Q17 through a 10 kΩ, and Q̄ goes to Q16 through a 10 kΩ.

The two inputs that stay free get new names. R, the reset input, goes to Q15, where input A was in Experiment 10. S, the set input, goes to Q18. The output of Gate 1 is called Q, and the output of Gate 2 is called Q̄, said “Q-bar”. The bar means “the opposite of Q”: in normal use one output is 1 and the other is 0. In Experiment 12 the threshold comparator's OUT drives R, and the trigger comparator's OUT drives S. In this experiment, the function generator drives the free leg of each input's 10 kΩ. 0 V gives a 0, and 5 V gives a 1.

## How the loop holds its state

The loop gives each gate one input from the other gate. Each gate still follows the NOR rule from Experiment 10: its output is 1 only when both of its inputs are 0. Figure 11-3 shows the latch while S is at 1, and below it again after S returns to 0. A transistor that is off is pale, and green arrows show where current flows. The list gives the reason for each change, in order.

![Two copies of the latch schematic, one above the other. Top: R equals 0, S equals 1. Q18 and Q17 are dark, Q15 and Q16 are pale. Green arrows run down through Gate 2's 1 kilohm, labelled 5 milliamps, and into the collectors of Q18 and Q17. Q equals 1 at 4.6 volts, Q-bar equals 0 at 0.03 volts. Bottom: R equals 0, S equals 0. Only Q17 is dark, with the green arrows through Gate 2's 1 kilohm and into Q17's collector. Q equals 1 at 4.6 volts, Q-bar equals 0 at 0.03 volts.](https://fullstackelectronics.com/experiments/img/11-set-hold.svg)

**Figure 11-3:** Top: S = 1 sets the latch. Bottom: S is back at 0, and Q stays at 1.

1.  S = 1 and R = 0. Current flows into Q18's base, and Q18 turns on. Q̄ falls to about 0.03 V: a 0.
2.  Q̄ is one input of Gate 1, and R is the other. Both are 0, so Q15 and Q16 are off, and Q rises: a 1.
3.  Q is one input of Gate 2. So Q17 turns on as well, and the 5 mA of Gate 2 divides between Q17 and Q18.
4.  S returns to 0, and Q18 turns off. Q17 stays on, because Q still drives its base. So Q̄ stays at 0, and Gate 1 keeps Q at 1.

In the lower panel no input is at 1, and Q is still 1. Q holds Q17 on, and Q17 holds Q̄ at 0. Q̄ at 0 lets Gate 1 keep Q at 1. Each output keeps the other gate in its state, so the latch stays set until R changes it.

While the latch is set, a second pulse on S changes nothing, because Q̄ is already 0. In the timer, S comes from the trigger comparator's OUT. If noise makes that OUT rise twice, only the first rise changes the latch.

Figure 11-4 shows the same two steps for R.

![Two copies of the latch schematic, one above the other. Top: R equals 1, S equals 0. Q15 and Q16 are dark, Q18 and Q17 are pale. Green arrows run down through Gate 1's 1 kilohm, labelled 5 milliamps, and into the collectors of Q15 and Q16. Q equals 0 at 0.03 volts, Q-bar equals 1 at 4.6 volts. Bottom: R equals 0, S equals 0. Only Q16 is dark, with the green arrows through Gate 1's 1 kilohm and into Q16's collector. Q equals 0 at 0.03 volts, Q-bar equals 1 at 4.6 volts.](https://fullstackelectronics.com/experiments/img/11-reset-hold.svg)

**Figure 11-4:** Top: R = 1 resets the latch. Bottom: R is back at 0, and Q stays at 0.

1.  R = 1 and S = 0. Q15 turns on, and Q falls to a 0.
2.  Q at 0 turns Q17 off. Q18 is also off, because S is 0. So Q̄ rises to a 1.
3.  Q̄ drives Q16's base, and Q16 turns on as well.
4.  R returns to 0, and Q15 turns off. Q16 stays on, because Q̄ drives its base. So Q stays at 0.

Compare the lower panels of Figures 11-3 and 11-4. In both, S and R are 0. In Figure 11-3 Q is 1, and in Figure 11-4 Q is 0. The inputs are the same and the outputs are opposite, because the latch records which input was 1 last. That record is the one bit of memory that the timer needs.

## Build Gate 2

Figures 11-3 and 11-4 showed how the loop stores one bit. Gate 2 goes in the upper block, straight above Gate 1, in the same columns 28 to 33. In this block the outer top rail is ground and the inner top rail is +5 V. So Q17 and Q18 stand in row d with their flat faces towards the near edge. Their emitters go up to the outer top rail, and their pull-up goes to the inner top rail.

Two new 10 kΩ resistors connect the gates. Each one crosses the channel one column skewed. One brings Q, the lower strip of column 28, to Q17's base in column 29. The other brings Q̄, the upper strip of column 33, to Q16's base in column 32. Input B's 10 kΩ comes out, because Q16's base now takes Q̄.

The function generator drives both inputs of the latch, so neither input resistor goes in a rail. R is input A of Experiment 10. Its 10 kΩ already stands in 29j with its free leg over the bottom rails, as the oscilloscope test of Experiment 10 left it. S's 10 kΩ stands in Q18's base strip at 32a, with its free leg over the top rails. Figure 11-5 shows the finished latch.

[![The breadboard drawn 40 columns wide, with both comparators, the divider, the tap jumpers and the two 1 kilohm ramp resistors faded. The whole latch is in colour. In the lower block, columns 28 to 33: the NOR gate of Experiment 10, Q15 and Q16 with their emitter jumpers, the green collector jumper 28i to 31i and the 1 kilohm pull-up from 31j to the outer bottom rail. Input B's 10 kilohm is gone. In the upper block straight above the NOR gate: Q17, a 2N3904, at 28d to 30d and Q18 at 31d to 33d, both with their flat faces towards the near edge. A green jumper joins 30b and 33b. Blue jumpers run from 28a and 31a straight up to the outer top rail. A 1 kilohm pull-up runs from 33a to the inner top rail. Two 10 kilohm resistors cross the centre channel one column skewed: from 28f to 29e, labelled Q to Q17, and from 33e to 32f, labelled Q-bar to Q16. S's 10 kilohm stands in 32a and rises over the top rails, leaning left, labelled S: 10 kilohm, free leg for the generator. R's 10 kilohm stands in 29j and leans down over the bottom rails, labelled R: 10 kilohm, free leg for the generator.](https://fullstackelectronics.com/experiments/img/11-breadboard-latch.svg)](https://fullstackelectronics.com/experiments/img/11-breadboard-latch.svg)

**Figure 11-5:** The latch in columns 28 to 33, with Gate 2 above Gate 1. R and S have free legs for the generator.

1.  **Switch off** the 5 V supply and the generator.
2.  **Unclip the generator's red lead** from the free leg of A's 10 kΩ. Leave its black lead on the top ground rail at column 7. A's 10 kΩ keeps its free leg. This resistor is now R. The oscilloscope probe stays on 31f.
3.  **Remove input B's 10 kΩ** from 32j and the inner bottom rail.
4.  **Fit Q17.** Put a 2N3904 in 28d, 29d and 30d, with its flat face towards the near edge. Its legs read emitter, base, collector from left to right.
5.  **Fit Q18** in 31d, 32d and 33d, the same way round.
6.  **Join the collectors.** Fit a jumper from 30b to 33b.
7.  **Connect Q17's emitter to ground.** Fit a jumper from 28a to the outer top rail at column 28.
8.  **Connect Q18's emitter to ground.** Fit a jumper from 31a to the outer top rail at column 31.
9.  **Fit the 1 kΩ pull-up** from 33a to the inner top rail, the +5 V one.
10. **Connect Q to Q17.** Fit a 10 kΩ from 28f to 29e, across the centre channel.
11. **Connect Q̄ to Q16.** Fit a 10 kΩ from 33e to 32f, across the centre channel.
12. **Fit S's 10 kΩ.** Put one leg in 32a. Bend the resistor so that its free leg stands over the top rails, leaning left.

## Set, hold and reset the latch

The latch is complete. The two channels of the function generator take the place of the two comparators. Channel 1 drives S with a 1 ms pulse every 10 ms. Channel 2 drives R with the same pulse, 5 ms later. Oscilloscope channel 1 shows S, through a BNC T-piece on generator channel 1. Channel 2 shows Q, and channel 3 shows Q̄. R is not on the oscilloscope: Q falls at the start of each R pulse, so Q shows where R is. Figure 11-6 shows the connections.

[![The breadboard with everything from Figure 11-5 faded except the R and S resistors, which stand with their free legs out. R's 10 kilohm stands in 29j and leans down over the bottom rails, with a ring on its free leg labelled R: generator channel 2 red lead. S's 10 kilohm stands in 32a and rises over the top rails, with a ring on its free leg labelled S: generator channel 1 red lead. Rings also mark oscilloscope channel 2's tip on Q at 31f and its ground on the bottom ground rail at column 37, oscilloscope channel 3's tip on Q-bar at 30e and its ground on the outer top rail at column 35, and generator channel 2's black lead on the bottom ground rail at column 34. A faded ring marks generator channel 1's black lead on the top ground rail at column 7.](https://fullstackelectronics.com/experiments/img/11-breadboard-scope.svg)](https://fullstackelectronics.com/experiments/img/11-breadboard-scope.svg)

**Figure 11-6:** Generator channel 1 on S and channel 2 on R. Oscilloscope channel 2 on Q and channel 3 on Q̄.

1.  **Set generator channel 1** to a pulse at 100 Hz, 1 ms wide. Set its high level to 5 V and its low level to 0 V. Keep its load setting at HiZ.
2.  **Set generator channel 2** to the same pulse, with a delay of 5 ms.
3.  **Connect generator channel 1.** Clip its red lead onto the free leg of S's 10 kΩ. Its black lead stays on the top ground rail at column 7.
4.  **Connect generator channel 2.** Clip its red lead onto the free leg of R's 10 kΩ, and its black lead onto the bottom ground rail at column 34.
5.  **Connect the second probe** to oscilloscope channel 3. Put its tip on 30e and its ground clip on the outer top rail, the ground one, at column 35. The channel 2 probe stays on 31f, with its ground clip on the bottom ground rail at column 37.
6.  **Set the oscilloscope:** channels 1, 2 and 3 at 1 V/div, and the timebase at 5 ms/div. Put the ground markers of all three channels at the same height, near the bottom of the screen. Trigger on channel 1, rising, at 2.5 V.
7.  **Add the measurements.** In the Measure menu, add Pk-Pk and Period for channel 1, and Top for channels 2 and 3. Top is the level of the flat top of a trace, here the level of a 1.
8.  **Switch on** the 5 V supply and both generator channels.

Before you read a level, make sure that each channel's probe setting agrees with its probe. A ×10 probe on a channel set to ×1 shows one tenth of the voltage. A 1 at 4.6 V then reads 0.46 V and looks like a 0. On my first build of this latch, one output seemed to stay at 0 for this reason. The circuit was correct.

![Oscilloscope with channels 1, 2 and 3 at 1 volt per division and the same ground marker near the bottom, 5 milliseconds per division, triggered on channel 1 rising. The yellow trace, S, shows a short pulse from 0 to 5 volts every 10 milliseconds. The magenta trace, Q, rises to about 4.6 volts at each S pulse and falls to near 0 volts 5 milliseconds later. The cyan trace, Q-bar, is the mirror image of Q: near 0 volts while Q is high and about 4.6 volts while Q is low. The measurements under the traces read Pk-Pk 5.20 volts and period 10.00 milliseconds on channel 1, Top 4.60 volts on channel 2 and Top 4.64 volts on channel 3.](https://fullstackelectronics.com/experiments/img/11-latch-hold.png)

**Figure 11-7:** S in yellow, Q in magenta and Q̄ in cyan. Q falls at the start of each R pulse, 5 ms after S.

Q rises at the start of each S pulse. The S pulse ends 1 ms later, and Q stays at 1 for the next 4 ms, while S and R are both 0. Then the R pulse resets the latch, and Q stays at 0 until the next S pulse. So Q is high for 5 ms in each 10 ms. Q̄ is the opposite of Q all the time. The table gives the four states in each 10 ms period, with the expected levels.

| State            | Time       | S   | R   | Q      | Q̄      |
|------------------|------------|-----|-----|--------|--------|
| Set              | 0 to 1 ms  | 1   | 0   | 4.6 V  | 0.03 V |
| Hold after set   | 1 to 5 ms  | 0   | 0   | 4.6 V  | 0.03 V |
| Reset            | 5 to 6 ms  | 0   | 1   | 0.03 V | 4.6 V  |
| Hold after reset | 6 to 10 ms | 0   | 0   | 0.03 V | 4.6 V  |

The two hold rows have the same inputs and opposite outputs. The difference is the bit that the loop stores. On my current board the Top measurements in Figure 11-7 read 4.60 V on Q and 4.64 V on Q̄. The section “Why the high is 4.6 V” explains why it is lower than in Experiment 10.

If Q follows S and falls as soon as the S pulse ends, check the two 10 kΩ resistors across the centre channel. One must go from 28f to 29e, and the other from 33e to 32f. If an output shows a slow wave of a few tenths of a volt where a 1 must be, that output is not connected. Check that each lead is tight in its clip, and that each pull-up is in its +5 V rail.

The time from an S pulse to the next R pulse sets how long Q stays high.

1.  **Set the delay of generator channel 2** to 2 ms. Expect Q to stay high for 2 ms in each 10 ms.
2.  **Set the delay back** to 5 ms.

In the timer, the capacitor sets that time. S rises when the capacitor voltage falls below 1/3 of the supply, and R rises when it passes 2/3. The latch holds Q at 1 while the capacitor charges from one level to the other.

## Why the high is 4.6 V

The table expects a 1 of about 4.6 V on both outputs. In Experiment 10 a 1 at OUT read 5.003 V on my current board, but there OUT drove only the multimeter. In the latch, Q also drives Q17's base through a 10 kΩ, and the current for that base flows through the pull-up of Gate 1. Figure 11-8 shows that path while the latch holds the set state.

![The latch schematic held set, with R equals 0 and S equals 0. Q15, Q16 and Q18 are pale, Q17 is dark. A thin green arrow labelled 0.39 milliamps runs down beside Gate 1's 1 kilohm. A second thin green arrow runs down the wire that takes Q to Q17's 10 kilohm, and the base of Q17 is labelled base: 0.7 volts. Thicker green arrows labelled 5 milliamps run down through Gate 2's 1 kilohm and into Q17's collector. Q equals 1 at 4.6 volts, Q-bar equals 0 at 0.03 volts.](https://fullstackelectronics.com/experiments/img/11-high-load.svg)

**Figure 11-8:** The latch holding the set state. The two thin green arrows show Q17's base current, 0.39 mA, through Gate 1's 1 kΩ and along Q to Q17's 10 kΩ.

1.  Q15 and Q16 are off. So all the current through Gate 1's 1 kΩ goes on along Q and through Q17's 10 kΩ into its base.
2.  Q17's base sits about 0.7 V above ground. So the two resistors, 11 kΩ in total, have about 5 V − 0.7 V = 4.3 V across them.
3.  The current is 4.3 V / 11 kΩ = 0.39 mA.
4.  That current puts 0.39 mA × 1 kΩ = 0.39 V across the pull-up. So Q sits at 5.00 V − 0.39 V = 4.6 V.

In the reset state Q̄ drives Q16 in the same way, so a 1 on Q̄ is also about 4.6 V. That is still far above the band from 0.60 V to 1.10 V where a transistor switch from Experiment 3 changes state. The 0.39 mA into Q17's base is more than five times the 0.07 mA that its 5 mA collector current needs. So the 0 on Q̄ stays near 0.03 V.

Each further input on Q takes its own base current through the same 1 kΩ, and the 1 falls again. This is a weak point of resistor-transistor logic: one output can drive only a few inputs. Experiment 12 connects more inputs to Q and Q̄, so it must keep their base currents small.

## S and R at 1 together

The pulses so far never put S and R at 1 at the same time. Figure 11-9 shows what happens then.

![The latch schematic with R equals 1 and S equals 1. Q15 and Q18 are dark, Q16 and Q17 are pale. Green arrows labelled 5 milliamps run down through both 1 kilohm pull-ups and into the collectors of Q15 and Q18. Q equals 0 at 0.03 volts and Q-bar equals 0 at 0.03 volts.](https://fullstackelectronics.com/experiments/img/11-both.svg)

**Figure 11-9:** S and R both at 1. Q15 and Q18 are on, so both outputs are 0.

Each gate has one input at 1, so both outputs are 0. Q and Q̄ are then the same, and the bar no longer means “the opposite of Q”. The next state depends on the input that returns to 0 last. If S returns to 0 first, R is still 1 and resets the latch. If R returns to 0 first, S sets it. If both return to 0 at the same moment, both outputs start to rise together. Small differences between the transistors then decide the state, so nobody can say in advance which state follows.

Wider pulses that overlap show this on the oscilloscope. S rises first, and R rises 1 ms later. S also falls first, so R resets the latch.

1.  **Set both generator channels** to pulses 3 ms wide. Set the delay of channel 2 to 1 ms. Set the oscilloscope timebase to 2 ms/div, and keep its other settings.

![Oscilloscope with channels 1, 2 and 3 at 1 volt per division and the same ground marker near the bottom, 2 milliseconds per division, triggered on channel 1 rising. The yellow trace, S, shows a pulse from 0 to 5 volts, 3 milliseconds wide, every 10 milliseconds. At the start of each S pulse the magenta trace, Q, rises to about 4.6 volts and falls back to near 0 volts 1 millisecond later. The cyan trace, Q-bar, falls to near 0 volts at the start of each S pulse and rises to about 4.6 volts when S falls, 3 milliseconds later. Between 1 and 3 milliseconds after each S rise, both Q and Q-bar are near 0 volts. The measurements under the traces read Pk-Pk 5.24 volts and period 10.00 milliseconds on channel 1, Top 4.64 volts on channel 2 and Top 4.64 volts on channel 3.](https://fullstackelectronics.com/experiments/img/11-both-overlap.png)

**Figure 11-10:** S in yellow, Q in magenta and Q̄ in cyan. R, not on the oscilloscope, is high from 1 to 4 ms. S falls first, so R resets the latch.

S sets the latch at 0 ms, and Q rises. At 1 ms R rises too. Both outputs are then 0, so neither trace is high. At 3 ms S falls while R is still 1, so Q̄ rises and the latch is reset. When R falls at 4 ms, Q stays at 0. On my current board the oscilloscope measured Q high for 1 ms in each 10 ms, and Q̄ low for 3.00 ms.

1.  **Set the delay of channel 2** to 9 ms. R now rises 1 ms before S and falls 2 ms after S rises, while S is still 1. Expect Q to rise when R falls, and to stay at 1 until the next R pulse.
2.  **Switch off** both generator channels and the 5 V supply.

The timer never puts S and R at 1 together. Experiment 9 showed that the trigger comparator's OUT is high only while the ramp is below 1/3 of the supply. The threshold comparator's OUT is high only while the ramp is above 2/3. In Experiment 12 one capacitor voltage drives both comparators, and it cannot be below 1/3 and above 2/3 at the same time.

#### In the NE555, S has priority

The NE555 has a latch at the same place. The Texas Instruments datasheet for the NE555 (SLFS022K) describes it. A trigger voltage below 1/3 of the supply sets the latch, and a threshold voltage above 2/3 resets it. Its function table also gives the case with both at once. With the trigger below 1/3, the output is high, whatever the threshold voltage is. So in the chip, S has priority over R.

The latch in this experiment has no priority, and both of its outputs go to 0. In a timer where one capacitor drives both pins, the case does not occur. It can occur when a circuit outside the chip drives the trigger pin. Then a trigger pulse that lasts longer than the timing period keeps the output high until the pulse ends.

#### The first latch had two vacuum tubes

In 1918 William Eccles and Frank Jordan, two physicists in London, filed a British patent. Their circuit had two vacuum tubes. The output of each tube drove the input of the other tube, as Q and Q̄ do in this latch. A pulse changed its state, and the state then stayed. They published the circuit in 1919 as a “trigger relay”. About twenty years later, the same circuit stored bits in Colossus and ENIAC, two of the first electronic computers.

## Quick check

Three questions on this experiment. They ask about the hold state, what keeps the latch in its state, and why its 1 is lower than in Experiment 10.

1\. With S and R both at 0, Q…

is always 0

keeps the level that the last pulse on S or R gave it

falls slowly towards 0 V

S = 0 and R = 0 is the hold state. Each output keeps the other gate in its state. So Q stays at 1 after a pulse on S, and at 0 after a pulse on R.

2\. After S returns to 0, Q17 stays on because…

Q is at 1 and drives Q17's base through its 10 kΩ

S left a charge on Q17's base

Q̄ drives Q17's collector

Q stays at 1 while Q̄ is 0, and Q drives about 0.39 mA into Q17's base. Q17 then keeps Q̄ at 0. Without the 10 kΩ from 28f to 29e, the latch loses its state as soon as S returns to 0.

3\. A 1 in the latch is about 4.6 V, lower than the 5.003 V of Experiment 10, because…

the second gate puts a second 1 kΩ in series with the first

Q17 pulls the supply down to 4.6 V

each output also drives a base, and that current puts about 0.39 V across the pull-up

About 0.39 mA flows from +5 V through the 1 kΩ and the 10 kΩ into the next gate's base. It puts about 0.39 V across the 1 kΩ, so the 1 sits at about 4.6 V.

## Before moving on

Two NOR gates, with the output of each on an input of the other, make an SR latch. A pulse on S sets Q to 1, and a pulse on R resets it to 0. With both inputs at 0, the latch holds its last state. Its 1 is about 4.6 V and its 0 about 0.03 V. The latch stays on the board, in columns 28 to 33, Gate 2 above Gate 1.

The board now holds every block of the timer: two comparators, the divider that sets their thresholds, and the latch. [Experiment 12: The Swap](https://fullstackelectronics.com/experiments/12-the-swap.html.md) connects the trigger comparator's OUT to S and the threshold comparator's OUT to R. It adds the timing resistors and capacitor and two more transistors, and the board then runs as a timer.